Showing papers by "Actel published in 2009"

Single event transient mitigation and measurement in integrated circuits

Abstract: A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements.

Improving Simulated Annealing-Based FPGA Placement With Directed Moves

Abstract: Simulated annealing remains a widely used heuristic for field-programmable gate array placement due, in part, to its ability to produce high-quality placements while accommodating complex objective functions. This paper discusses enhancements to annealing-based placement which improve upon both quality and run-time. Specifically, intelligent strategies for selecting and placing cells are interspersed with traditional random moves during an anneal, allowing the annealer to converge more quickly and to attain better quality with less statistical variability. For the same amount of computational effort, the contributions discussed in this paper consistently improve both critical path delay and wire length compared to traditional annealing perturbations.

Flash-based fpga with secure reprogramming

Abstract: A flash-based programmable integrated circuit includes programmable circuitry, a flash memory array coupled to the programmable circuitry for configuring it, flash programming circuitry for programming the flash memory array, and an on-chip intelligence, such as a microcontroller or state machine, coupled to the programming circuitry to program the flash memory from off-chip data supplied via an I/O pad, or to refresh the data stored in the flash memory to prevent it from degrading.

ASIC versus antifuse FPGA reliability

Abstract: ASICs are generally accepted as the highest reliability for custom circuits as they do not have the overhead to personalize them when compared to an FPGA. However, it is this overhead in FPGAs that allow them to be testable before personalization by the user, that makes them testable to a much higher degree than ASICs. Actual data from burn-in is compared between an ASIC and an RTAXS FPGA indicating that the FPGA is an order of magnitude more reliable than the ASIC.

Array and control method for flash based fpga cell

Abstract: A push-pull non-volatile memory array includes memory cells with an n-channel non-volatile pull-down transistor in series with a p-channel volatile pull-up transistor. A non-volatile transistor row line is associated with each row of the array and is coupled to the control gates of each n-channel non-volatile pull-down transistor in the row. A volatile transistor row line is associated with each row of the array and is coupled to the control gates of each p-channel volatile pull-up transistor in the row with which it is associated. A column line is associated with each column in the array and is coupled to the source of each p-channel volatile pull-up transistor in the column with which it is associated.

Flexible carry scheme for field programmable gate arrays

Abstract: A fast, flexible carry scheme for use in clustered field programmable gate array architectures is described. Each cluster has a cluster carry input node, a cluster carry output node, a cluster carry output circuit having an output coupled to the cluster carry output node, a first input coupled to the cluster carry input node, and a second input and a plurality of logic modules each comprising a logic function generator circuit coupled to a carry circuit. The logic modules are coupled in a series carry arrangement between the cluster carry input node and the second input of the cluster carry output circuit such that the least significant bit of an arithmetic logic circuit can be programmably placed in any of the logic modules.

FPGA technology mapping with encoded libraries andstaged priority cuts

Abstract: Technology mapping is an important step in the FPGA CAD flow in which a network of simple gates is converted into a network of logic blocks. We consider enhancements to a traditional LUT-based mapping algorithm for an FPGA comprised of logic blocks which implement only a subset of functions of up to k variables--specifically, the logic block is a partial LUT, but it possesses more inputs than typical LUTs. Numerical results are presented to demonstrate the efficacy of our proposed techniques using real circuits mapped to a commercial FPGA architecture.

SET characterization and mitigation in RTAX-S antifuse FPGAs

Abstract: Heavy-ion test results utilizing novel test methodologies of non-volatile antifuse-based FPGAs are presented and discussed. In particular, the programmable architectures in the RTAX-S FPGA-family including the I/O structures, and the FPGA core were tested and their cross-sections measured. Previously available SET mitigation solution based on SET filtering was implemented on the RTAX-S test designs and their efficacy proven to reduce the saturation cross-section and increase the LET threshold of the mitigated test designs.

Field programmable gate array architecture having Clos network-based input interconnect

Abstract: A cluster internal routing network for use in a programmable logic device with a cluster-based architecture employs a Clos network-based routing architecture. The routing architecture is a multi-stage blocking architecture, where the number of inputs to the first stage exceeds the number of outputs from the first stage.

Physical optimization for FPGAs using post-placement topology rewriting

Abstract: Due to poor correlations between pre- and post-placement timing analysis, many post-placement optimization strategies have been proposed for the FPGA CAD flow to improve circuit performance. Typically, these methods depend on logic duplication or decomposition methods combine together with incremental placement.Circuit rewriting has proven to be a useful optimization strategy, but is typically applied during the technology mapping step of the FPGA CAD flow. While beneficial, rewriting either before or after technology mapping must rely on circuit depth rather than post-placement delays for timing optimization.In this paper, we show that circuit rewriting can also be used as a post-placement optimization for FPGAs. We present a post-placement optimization based on circuit rewriting which is guided by post-placement timing analysis. We replace, or rewrite, cones of logic on critical paths to improve the timing performance of a circuit. Our method is integrated with incremental placement to ensure valid placements and to guarantee that our timing analysis remains accurate throughout our proposed rewriting method. The key to our method is the ability to quickly determine if an alternative topology of LUTs is suitable for the replacement of a cone of logic on a critical path.We have implemented our proposed method in a commercial FPGA CAD flow. Experimental results demonstrate that the application of our rewriting algorithm can improve the routed timing performance of a design by 3.1% on average and by as much as 37.9% when applied to a set of 136 industrial designs.

Clustered field programmable gate array architecture

Abstract: A logic cluster for a field programmable gate array integrated circuit device is disclosed. The cluster comprises a plurality of functional blocks and three levels of routing multiplexers. External signals enter the logic cluster primarily at the third level multiplexers with a few signals entering at the second level. Combinational outputs are fed back into the first and second level multiplexers while sequential outputs are fed back into the third level multiplexers. The logic function generators have permutable inputs with varying propagation delays. Routing signals between the first and second level multiplexers are grouped into speed classes and coupled to first level multiplexers associated with different logic function generators according to their speed class. Second and third level multiplexers are organized into groups such that routing signals between the second and third level multiplexers can be localized within the area occupied by the group. Groups are pitch matched to logic function generators to optimize and modularize area. Provision is made for global and local control of the sequential elements.

Cycling impact on the Gm degradation and GIDL current of 65nm 2T-embedded Flash memory

Abstract: Abnormal Gm degradation and GIDL current in the Uniform Channel Program and Erase (UCPE) floating gate 2 transistor (2T)-embedded flash cell (eFlash) is investigated. Severe charge trapping and de-trapping at the floating gate to junction overlap area lead to the endurance failure and cell current degradation. Control Gate (CG)-Select Gate (SG) Inter-junction trapping further degrades endurance and GIDL due to enhanced field and deeply depleted inter-junction. High temperature retention bake showed the charge relaxation and subsequent failure in the programmed cells. In this paper, we report both Gm and GIDL improvement of 2T eFlash memory with optimized gate-sidewall and extra thermal steps within the constraint of embedding flash process in the 65nm standard logic process.