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Showing papers by "Freescale Semiconductor published in 1983"


Patent
25 Mar 1983
TL;DR: In this paper, a bus master is prevented from utilizing a communication bus during a current sample interval if the utilization rate of the communication bus (18) during the immediately preceding sample interval exceeded a selected limit.
Abstract: A bus master (14) is prevented from utilizing a communication bus (18) during a current sample interval if the utilization rate of the communication bus (18) during the immediately preceeding sample interval exceeded a selected limit.

30 citations


Patent
18 Apr 1983
TL;DR: In this paper, the processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the operation word to a particular Coprocessor designated by a Coproprocessor Identity field in the Operation word.
Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires the Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.

28 citations


Patent
18 Feb 1983
TL;DR: In this paper, a three state gate with an output capable of assuming an active high, an active low, or a high impedance state is disclosed that eliminates a glitch in the output during the transition from the high-imperceptible state to the active high.
Abstract: A three state gate having an output capable of assuming an active high, an active low, or a high impedance state is disclosed that eliminates a glitch in the output during the transition from the high impedance state to an active high. An output means includes a first transistor for supplying current to the output and a second transistor for draining current from the output. A phase splitting means determines the conductivity of the first and second transistors. A logic means is responsive to both an input signal and an output enable signal and is coupled to the phase splitting means. The logic means includes a level setting means that insures that the second transistor is not conductive during the transition of the output from the active high to the high impedance state.

7 citations