Showing papers by "General Dynamics published in 2000"

A High Performance Reconfigurable Elliptic Curve Processor for GF(2m)

Abstract: This work proposes a processor architecture for elliptic curves cryptosystems over fields GF(2m). This is a scalable architecture in terms of area and speed that exploits the abilities of reconfigurable hardware to deliver optimized circuitry for different elliptic curves and finite fields. The main features of this architecture are the use of an optimized bit-parallel squarer, a digit-serial multiplier, and two programmable processors. Through reconfiguration, the squarer and the multiplier architectures can be optimized for any field order or field polynomial. The multiplier performance can also be scaled according to system's needs. Our results show that implementations of this architecture executing the projective coordinates version of the Montgomery scalar multiplication algorithmcan compute elliptic curve scalar multiplications with arbitrary points in 0.21 msec in the field GF(2167). A result that is at least 19 times faster than documented hardware implementations and at least 37 times faster than documented software implementations.

A high-performance reconfigurable elliptic curve processor for GF(2m)

Abstract: This work proposes a processor architecture for elliptic curves cryptosystems over fields GF(2 m ) This is a scalable architecture in terms of area and speed that exploits the abilities of reconfigurable hardware to deliver optimized circuitry for different elliptic curves and finite fields The main features of this architecture are the use of an optimized bit-parallel squarer, a digit-serial multiplier, and two programmable processors Through reconfiguration, the squarer and the multiplier architectures can be optimized for any field order or field polynomial The multiplier performance can also be scaled according to system's needs Our results show that implementations of this architecture executing the projective coordinates version of the Montgomery scalar multiplication algorithm can compute elliptic curve scalar multiplications with arbitrary points in 021 msec in the field GF(2 167 ) A result that is at least 19 times faster than documented hardware implementations and at least 37 times faster than documented software implementations

Data storage housing

Abstract: An array module containing an array of electronic units is mounted in an installation frame. The electronic units can be mounted by rails in a hermetically sealed array housing and blind-mate connectors can connect the units to a rear plate. Blind-mate connectors also can connect the rear plate to the installation frame for external connection. A plurality of resilient mounts are fastened to the installation frame to protect the frame and storage array module from external shock. A thermal transfer mechanism transfers thermal energy between the electronic units and a region exterior to the installation frame. The electronic units can be enclosed in hermetically sealed chambers having side rails for rigidly fastened to the unit and a resilient support connecting the side rails to at least one of the covers of the hermetically sealed chamber. Thermal rails can be permanently mounted by a plurality of resilient thermal conductors to either the side rails or one of the covers, and a fastener removably mounts the thermal rails to the other of the side rails or one of the covers so that the thermal rails and resilient thermal conductors provide conduction of thermal energy between the side rails and one of the covers.

Lane detection using histogram-based segmentation and decision trees

Abstract: A vision system for intelligent vehicles is proposed here. The system exploits the characteristics of the gray level histogram of the road to detect lane markers. Each lane marker is then analyzed using a decision tree, and finally the relations between lane markers are analyzed to create structures defining the lane boundaries. The resulting system also generates images that can be used as preprocessing stages in lane detection, lane tracking or obstacle detection algorithms. The system runs in realtime at rates of about 30 Hz.

Dynamic hardware resource manager for software-defined communications system

Abstract: A hardware resource manager ( 18 ) dynamically allocates hardware resources in a software-defined communications system. The hardware resource manager ( 18 ) creates a specification of required hardware resources ( 300 ) necessary for executing a system application. The hardware resource manager ( 18 ) then creates a list of candidate hardware resources ( 306 ) from the plurality of available hardware resources in response to an application creating its own abstract resource specification ( 78 ) of required hardware resources. The hardware resource manager ( 18 ) then maps each required hardware resource on the specification of required hardware resources to a least functional and most available candidate hardware resource on the list of candidate hardware resources in a manner that maximally preserves most functional and least available candidate hardware resources on the list of candidate hardware resources ( 316-326 ).

Method of regulating a flow of data in a communication system and apparatus therefor

Abstract: A flow of data ( 26 ) is regulated in a communication system ( 20 ). A data rate is established in each of a data source ( 24 ) and a data sink ( 28 ). The data ( 26 ) is transmitted by the data source ( 24 ) and written into a buffer ( 32 ) at the source data rate, then read from the buffer ( 32 ) and received by the data sink ( 28 ) at the sink data rate. The level ( 62 ) of data ( 26 ) in the buffer ( 32 ) is monitored, and a rate-control signal ( 74 ) is dispatched to either the data source ( 24 ) or sink ( 28 ) when it is determined the buffer data level ( 62 ) is decreasing or increasing while at a lower or upper data-level threshold ( 66, 68 ), respectively. One of the data rates is adjusted in response to a rate-control signal ( 74 ).

Methods and apparatus for error-resilient video coding

Abstract: Apparatus and methods are provided for encoding an input frame of a video sequence for transmission over a channel. The method and apparatus decompose the input frame into multiple subbands and divide the multiple subbands into multiple blocks corresponding to a region of the input frame. The blocks in the highest frequency subbands of the multiple blocks are selected based upon a luminance component of the input frame and the multiple blocks in the highest frequency subbands are classified into a multiple classes to provide a multiple class labels. The multiple class labels are collected to form a subband class map for each of the multiple blocks in the highest frequency subbands and a global class map is constructed from a majority evaluation of the subband map for each of the multiple blocks. The multiple blocks within the multiple subbands are grouped which have one of the class labels to form multiple subband class sequences.

Adjustable optical fiber grating dispersion compensators

Abstract: Adjustable optical fiber grating dispersion compensators. The invention provides a fully tunable dispersion compensator with a wide dynamic range. Dispersion compensators according to the invention are based on uniform fiber Bragg grating technology. Individual gratings are tuned so that the gratings, which normally operate in reflection mode, operate in transmission mode with the frequency of interest falling just outside a reflection band edge. Gratings are combined to provide broadband, or multiple-wavelength dispersion. Tuning is provided via transducers coupled to the gratings. A control system can be connected to the transducers to provide a control signal so that the frequencies of the gratings can be dynamically tuned. The control system operates by measuring signals from opto-electronic detectors. The signals are used to determine a fractional spectral power transmitted through a filter. The fractional spectral power is related to the amount of dispersion present in the optical path of the network.

Hermetically sealed plural disk drive housing

Abstract: A device for storage of electronic data has a sealed hard drive component that can be mounted directly to a circuit board. The device can house a plurality of individual hard drives in a stacked configuration. The stacked hard drives are encased within a hermetically sealed housing, the exterior of which has connectors suitable for mounting directly to a circuit board. At least two of the hard drives encased within the housing can be controlled by a single hard drive controller located inside or outside the housing.

Impedance-controlled connector

Abstract: An electrical connector assembly using conventional signal pins is adapted for use with impedance-controlled cables by dividing the body of the connector into one or more separate channels. Each channel is defined by a perimeter providing electrical shielding. A separate impedance-controlled wire or cable can be terminated at conventional signal pins installed in an insert located within a particular channel. A transition region between a connector plug or receptacle and an incoming wire or cable preserves the correct impedance characteristics of the cable.

Method and apparatus for accurately determining the position of satellites in geosynchronous orbits

Abstract: A method of determining the position of a satellite in a near geosynchronous orbit includes receiving at least one main lobe signal from an antenna on a first GPS satellite. A GPS signal, including GPS time and Doppler, is received from a pseudolite positioned on the Earth and an approximate position of each of a plurality of second GPS satellites is determined from an onboard almanac. Side lobe signals and accompanying noise are received from antennas on the plurality of second GPS satellites. The GPS signal and known sequential data bits are used for sorting or integrating the side lobe signals from the accompanying noise and the position of the satellite in a near geosynchronous orbit is determined using the one or more main lobe signals and the sorted side lobe signals.

Methods and apparatus for transmitting, receiving, and processing secure voice over internet protocol

Abstract: This disclosure describes systems and methods for processing voice data (110, 150) for secure transmission and secure receipt over a network, such as the Internet (250). The systems and methods include the processing of analog voice and digital information, including conversion of a voice signal into digital information (215) (or of digital information into a voice signal (290)) and transmission (240) (or receipt (265)) of digital information representing voice data over a network (250). The analog-to-digital conversion (215) (and digital-to-analog conversion (290)) is followed by coding (220) (or decoding (285)) digital information according to voice coding techniques, constructing (225) (or deconstructing (280)) a voice frame, and encrypting (230) (or decrypting (275)) digital information according to the encryption techniques. The transmission (240) (or receival (265)) of the digital information includes the creation (235) (or break down (270)) of a secure voice frame.

Methods and apparatus for object recognition and compression

Abstract: Apparatus and methods are provided for object recognition and compression. The apparatus ( 114 ) comprises an object processor ( 402 ) configured to receive the image ( 120 ) and synthesize a contour ( 404 ) of an object within the image ( 120 ) and a classification engine ( 406 ) configured to receive the contour ( 404 ) of the image ( 120 ) and recognize the object within the image as a member of a first object class if the object substantially meets first object criteria of the first object class that is at least partially related to the target-specific utility of the image. The apparatus ( 114 ) also comprises a multi-rate encoder ( 116 ) configured to compress a first region of the image ( 120 ) having said object recognized as said member of said first object class at a first coding rate, said first coding rate providing a first coding resolution of said first region that is greater than a second coding resolution provided by a second coding rate for the image.

Shock and acoustic mount

Abstract: A shock and acoustic mount for reducing transmission of forces between two relatively moveable members such as a mounted component and a supporting structure, providing a compressible fluid spring with large allowable relative movement of the mounted component and support structure. The mount comprises a casing, a piston shell with one end disposed in the casing and another end extending outside of the casing, and a piston housed in the piston shell, all relatively moveable in response to external axial forces. In one embodiment, the mount is filled with a compressible fluid, such as air, providing an air spring. The piston is sealingly bonded to the inner surface of the piston shell, the bond accommodating acoustic and vibration forces by deformation of the bond material. An annular seal between the piston shell and the casing accommodates large and shock forces. In another embodiment, passive damping is provided and a substantially incompressible second fluid is added to the casing, and there is one air spring inside the piston shell. In a third embodiment, an additional air spring is added outside the piston shell, and the response characteristics depend on the type of force applied to the mount.

A QoS performance measure framework for distributed heterogeneous networks

Abstract: In a distributed heterogeneous computing environment, users' tasks are allocated resources to simultaneously satisfy, to varying degrees, the tasks' different, and possibly conflicting, quality of service (QoS) requirements. When the total demand placed on system resources by the tasks, for a given interval of time, exceeds the resources available, some tasks will receive degraded service or no service at all. One part of a measure to quantify the success of a resource management system (RMS) in such a distributed environment is the collective value of the tasks completed during an interval of time, as perceived by the user, application, or policy maker. The flexible integrated system capability (FISC) ratio introduced here is a measure for quantifying this collective value. The FISC ratio is a multi-dimensional measure, and may include priorities, versions of a task or data, deadlines, situational mode, security, application- and domain-specific QoS, and dependencies. In addition to being used for evaluating and comparing RMS, the FISC ratio can be incorporated as part of the objective function in a system's scheduling heuristics.

Hardware resource identifier for software-defined communications system

Abstract: A hardware resource identifier ( 19 ) recognizes hardware resource dependencies in a multi-channel communications system. Initially, system communications domains (D 1 -D 4 ) in which system hardware resources are located are identified. Next, managed hardware resources, hardware resource groups and hardware resource group boundaries among the system hardware resources are identified. Association labels are then assigned to the system hardware resources to identify relationships, if any, between the system hardware resources and external hardware, to discern redundant resources within respective ones of the hardware resource groups, and to characterize dedicated coupling between individual ones of the system hardware resources. An abstract resource specification ( 78 ) is then interpreted to locate available system hardware resources, as organized into the system identified communications domains and the identified hardware resource groups, to enable maximum preservation of most functional and least available hardware resources during hardware resource allocation.

ARC discharge initiation for a pulsed plasma thruster

Abstract: Thermionic emission of electrons is utilized to initiate arc discharge in a pulsed plasma thruster.

Transmitter having programmable transmission parameters temporally aligned with payload and method therefor

Abstract: A software-defined radio (12) includes a transmitter (20) having any number of upstream modules (30) and any number of downstream modules (34). The upstream modules (30) perform signal processing on input signals (28), and the downstream modules (34) provide an RF interface for processed signals (58). The upstream modules (30) and downstream modules (34) couple to a common intra-transmitter signal transporter (32), which may be implemented as a bus. Programmable transmission parameters (60) which program the downstream modules (34) to generate a communication signal (18) exhibiting desired attributes such as frequency and keying are mingled with the processed input signal (58) in upstream modules (30) to preserve timing. The programmable transmission parameters (60) are extracted in downstream modules (34), and applied to the communication signal (18) at the timing specified by position relative to the processed input signal (58).

Burst communications method and apparatus

Abstract: A transmitter (400) offsets the transmission time and frequency of a burst transmission such that uncertainties in reception time and reception frequency are reduced. The transmitter includes an ephemeris store (454) that includes ephemeris data for one or more possible intended receivers (130). Orbits of possible intended receivers are propagated, and an intended receiver is selected. Transmission time offsets are generated as a function of transmitter location and intended receiver location. Transmission frequency offsets are substantially equal to a Doppler frequency derived from the transmitter velocity and the intended receiver velocity. Guard times and guard bands are reduced in size, resulting in greater available communications bandwidth and simpler receiver designs.

Symbol synchronizer for software defined communications system signal combiner

Abstract: A symbol synchronizer ( 100 ) is provided for a software-defined communications system ( 10 ). The symbol synchronizer ( 100 ), when integrated into either a pre- or post-detection diversity signal combiner ( 108, 208 ), enables highly accurate signal synchronization with minimal added system complexity. The symbol synchronizer ( 100 ) includes a single complex sliding window matched filter ( 102 ) for filtering an input digital signal with a match filtering function based on predetermined signal transfer function characteristics to average out receiver noise from the signal. A signal delay bank ( 84 ) includes a plurality of delay blocks each for delaying the digital signal filtered by the single matched filter for a predetermined number of samples. A complex correlator ( 88 ) correlates the digital signal filtered by the single complex sliding window matched filter ( 102 ) and delayed by the complex correlator ( 88 ) with a correlator reference signal, and selects an index of a path having a peak correlator value. As a result of such a configuration, the symbol synchronizer ( 100 ) is capable of determining symbol boundaries of channel signals in a multi-channel communications system to enable system signal measurement statistics and demodulated to be more accurately generated.

Communication system and method for multi-rate, channel-optimized trellis-coded quantization

Abstract: A communication system (20) employs fixed rate channel-optimized, trellis-coded quantization (COTCQ) at a plurality of diverse encoding bit rates. COTCQ is performed through a COTCQ encoder (40) and COTCQ decoder (54). The COTCQ encoder and decoder (40,54) each include a codebook table (62) having at least one codebook (64) for each encoding bit rate. Each codebook (64) is configured in response to the bit error probability of the channel (26) through which the communication system (20) communicates. The bit error probability influences codebooks through the calculation of channel transition probabilities for all combinations of codewords (90) receivable from the channel (26) given all combinations of codewords (90) transmittable through the channel (26). Channel transition probabilities are responsive to base channel transition probabilities and the hamming distances between indices for codewords within subsets of the transmittable and receivable codewords.

Radio transmission timing calibrator

Abstract: A signal calibrator (14) for a software-defined communications device (10) that enables device communications signals to be transmitted in a manner that maximally decouples the calibrator (14) from the device hardware (40), and that simplifies the design and reduces the cost of the communications device (10). The calibrator (14) includes a software modulator (16) for generating a nonstop stream of samples including zero valued samples and non-zero valued waveform bursts, and a software demodulator (18) connected to the software modulator (16) via a closed loop feedback path (20) that receives a nonstop stream of samples. The non-zero valued samples create radio emissions. The software demodulator (18) is for determining a timing error of the transmission sample and for transmitting a timing error correction value to the software modulator (16) via the closed loop feedback path (20). The timing error correction value enables the software modulator (16) to adjust a transmission time of a subsequent waveform burst to compensate for both unknown hardware delays and RF signal propagation delays.

Permanent magnet phase-control motor

Abstract: A motor has a rotor for controlling a parameter of an instrumentality, such as a blade or a blade flap. The rotor is positioned about the drive shaft of the instrumentality and rotates at the same average angular velocity of the drive shaft. The instrumentality is controlled by applying to the instrumentality a physical displacement signal that is generated by the phase relationship of the rotor of the motor with respect to the angular position of the drive shaft. A plurality of permanent magnets proximate the periphery of the rotor cooperate with a plurality of stator polepieces and electromagnetic coils. The current flowing through the coils is reversed each time that the rotor advances by the angular space of one permanent magnetic pole. The strength and polarity of the current flowing through the coils controls the direction and displacement of the rotor with respect to a neutral phasing of the rotor with respect to the drive shaft.

Dynamic DC balancing of a direct conversion receiver and method

Abstract: A direct conversion receiver includes a differential mode mixer with first and second DC coupled amplifier chains, the first and second amplifier chains are connected to the mixer for amplifying differential signals. A common mode offset correction circuit is coupled to the first and second amplifier chains so as to feedback correction signals that cause common mode DC offsets in the first and second amplifier chains to be equal and opposite. A differential mode offset correction circuit is coupled to the first and second amplifier chains so as to feedback correction signals that cause differential mode DC offsets in the first and second amplifier chains to be equal. The only solution for the two correction circuits is zero DC offset.

Multiple function bandwidth management systems

Abstract: Multiple function bandwidth management systems. Bandwidth-management systems for an optical network are easily assembled by concatenating a plurality of intelligent, miniaturized, bandwidth-management modules (BMM's) together. The BMM's subdivide the wide available spectrum into narrow band segments. Each individual BMM is designed to overcome loss and optimize dispersion, gain, and power or gain equalization for a few channels at a time. Each device includes optical connectors and filters, as well as any other components necessary to direct the band of optical channels through the device's optical path while passing other optical channels within the spectrum to additional devices which can be connected without disturbing existing bandwidth-management modules. Each BMM also includes a digital control module that operates the BMM in any one of a plurality of selectable operating modes.

Method and system for providing cryptographic services in a distributed application

Abstract: A data security system ( 26 ) provides cryptographic services in a multiprocessor platform ( 20 ) supporting a distributed application ( 22 ). The distributed application ( 22 ) includes a cryptographic object ( 52 ) that is executable exclusively on the data security system ( 26 ). An input interface object ( 102 ), a cryptographic function ( 90 ), and an output interface objection ( 104 ) form the cryptographic object ( 52 ). The data security system ( 26 ) includes a first processor element ( 92 ) for executing the input interface object ( 102 ), a second processor element ( 94 ) for executing the cryptographic function ( 90 ), and a third processor element ( 96 ) for executing the output interface object ( 104 ). The combination of data security system ( 26 ) and cryptographic object ( 52 ) ensures the separation of plain text data ( 46 ) from cipher text data ( 48 ).

Antenna mounting apparatus

Abstract: A mounting apparatus ( 100 ) suitable for retaining an antenna ( 112 ) includes a base ( 102 ) having magnetic sources ( 104 ) and ( 106 ) capable of providing varying magnetic forces. Magnet ( 104 ) retains the base against a metal surface ( 410 ), while an electronically controlled magnet ( 106 ) provides additional retention of the base ( 102 ) against the metal surface ( 410 ) when activated, thereby preventing movement of the base and antenna ( 112 ).

Kinetic energy penetrator

Abstract: A subcaliber kinetic energy penetrator has first and second portions formed of dense material and secured to each other. The first portion, located ahead of the second portion preferably represents between 9% and 15% of the penetrator mass and a similar percentage of the combined lengths of the two portions. The first portion is formed of a material effective to produce a relatively large hole in an explosive reactive armor faceplate. The second portion is preferably formed from material selected to best perforate basal armor.

Method for multiplication in galois fields using programmable circuits

Abstract: A scalable multiplier architecture (36) for a Galois field GF(2k) is implemented in a programmable circuit. The multiplier architecture has m-bit super-serial multiplier (32) having m processors (SS), where m is less than k. The super-serial multiplier emulates in (k/m) cycles one cycle of a k-bit serial multiplier (30) for multiplying one bit of an element U by an element V of the Galois field, and repeats the one bit multiplication k times to produce a multiplication product of U and V.

Pressure vessel assembly

Abstract: A pressure vessel is provided for housing electronic components in an underwater environment and permitting connection of the components to signal transmission elements of a signal cable. The pressure vessel comprises a hollow steel shell defining an interior chamber adapted to house the electronic components. A layer of thermal-sprayed aluminum covers the shell. The shell has an opening adapted to pass the signal transmission elements into the interior chamber. A seal adapted to sealingly surround the transmission elements is disposed in the opening in the shell so that an outer peripheral surface of the seal contacts an inner peripheral surface of the opening in the shell for preventing moisture penetration into the interior chamber. The seal may be formed of epoxy and the outer peripheral surface have a plurality of compressible o-rings disposed in axially-spaced circumferential grooves for contacting the inner peripheral surface of the opening in the shell.