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Showing papers by "Samsung published in 1973"


Patent
01 Oct 1973
TL;DR: In this paper, a novel internal organization of an LSI memory chip for optimum refresh control is disclosed, which includes partitioning the N memory loops into S subgroups of 2n memory loops per subgroup, N = S2n, where n is a positive integer of 0 or greater.
Abstract: A novel internal organization of an LSI memory chip for optimum refresh control is disclosed. The chip is organized in a plurality of N similar memory loops in which the M data bits that are stored in each memory loop are serially shifted therethrough in an end-around fashion for the data reading, writing and refreshing operations. The novel internal organization includes partitioning the N memory loops into S subgroups of 2n memory loops per subgroup, N = S2n, where n is a positive integer of 0 or greater and then refreshing the 2n memory loops of each of the S subgroups at a refresh clock signal frequency FR that is a submultiple of the fundamental data clock signal frequency FD, FD = SFR, at which the normal data read/write operations are performed. A fundamental data clock signal source of frequency FD drives a refresh clock signal source that sequentially and continuously refreshes each of the N memory loops at the refresh clock frequency FR using the internal selection gates of the LSI memory chip rather than using the internal memory loop address decoder; this permits the refresh operation to be an entirely internal operation independent of external memory control.

29 citations


Patent
27 Aug 1973
TL;DR: In this article, the authors present an approach for precisely controlling the interval by which a conditioning signal on one conductor overlaps part of a unit enabling signal on another conductor in a dynamic storage semiconductor memory system.
Abstract: Apparatus for precisely controlling the interval by which a conditioning signal on one conductor overlaps part of a unit enabling signal on another conductor in a dynamic storage semiconductor memory system. The apparatus provides an initial conditioning signal pulse which extends beyond the desired interval of overlap with the unit enabling timing pulse and gates the conditioning signal with a selectively delayed inverse of the unit enabling pulse. This provides a resultant conditioning or precharging timing pulse that terminates at the end of a precise interval after the leading edge of the associated unit enabling timing pulse.

9 citations