Showing papers by "Samsung published in 1987"

Control circuit for liquid crystal rear-vision mirror

Abstract: A circuit for controlling a liquid crystal rear-vision mirror is disclosed The liquid crystal rear-vision mirror is equipped in an automobile to sense the amount of lights incident upon the mirror itself from a headlight of another automobile following behind When the level of incident lights goes higher than a pre-determined level, the circuit generates a pulse signal of a fixed period to make the liquid crystal shutter properly function so that the amount of said incident light reflecting from the mirror to the driver will be decreased to a level adequate to secure driving safety

Sense amplifier for high performance dram

Abstract: A sense amplifier and high performance DRAM, in combination, has in the DRAM at least one row of memory cells, whereby the memory cells of the row may be arranged in respective columns with memory cells of other rows. Each of the memory cells has a transistor and a capacitor connected serially between one of bit lines successively along the row and a fixed voltage source. Word lines are respectively connected to gates of the transistors of the memory cells for activating the memory cell selectively according to row address. The sense amplifier has a cross-coupled bistable flip-flop connecting the bit lines to each other in the row. A latch transistor connected to the flip-flop detects and amplifies a voltage difference between the bit lines. The bit lines are equalized and precharged with a reference voltage in response to a clock control signal. A cross-coupled pair of transistors also connecting the bit lines to each other transfer a charging voltage to the bit lines. A power-supply level voltage is supplied under the control of first and second control clock signals and boosted to a higher level charging voltage under the control of a third control clock signal, whereby the storage capacitors of the memory cells are charged to the higher voltage.

Column redundancy circuit for CMOS dynamic random access memory

Abstract: A dynamic random access memory for substituting a normal column line coupled for faulty normal memory cells for a spare column line coupled to defect-free spare memory cells with a latch having a master fuse and an input terminal coupled to a reset clock, a spare column decoder enabling or disabling the spare column line with the output of the latch and the selective input of either true column address signals or complement column address signals and a plurality of normal column decoders enabling or disenabling normal column lines with the column address signals addressing a specified normal column line under the control of the ouptut of the spare column decoder.

Speaking fire alarm system

Abstract: A speaking fire alarm system for not only giving an alarm in voice on an occurrence of a fire but also providing some information necessary for coping with the situations. The system includes a temperature sensor for sensing a surrounding temperature and providing a voltage responsive to the temperature sensed, comparator means for comparing the voltage supplied from the temperature sensor with a reference voltage and thereby providing a logic signal in accordance with its comparison, a central processing unit for receiving the logic signal from the buffer, thereby deciding the occurrence of the fire and providing both a fire alarm signal and message data according to an emergent situation, a voice synthesizer for providing address signals in accordance with the message data supplied from the central processing unit and also providing quantized voice messages which are synthesized from voice data received, voice memory for providing again to the voice synthesizer the voice data which is in advance stored in adequate format responsive to the address signals supplied from the voice synthesizer, voice output amplifying means for receiving the quantized voice messages supplied from the voice synthesizer for reshaping to smooth waveforms and amplifying to an adequate level, a host computer having a control program for controlling a plurality of slave fire control systems which are coupled to the host computer itself for detecting the fire alarm signal from each central processing unit and providing the fire alarm signal to remaining slave fire alarm systems.

A Study on the Three-Dimensional Analysis of the Transient Temperature Distribution in Gas Tungsten Arc Welding:

Abstract: The transient temperature distribution in the gas tungsten arc (GTA) welding process was analysed by employing a three-dimensional finite element model. In the formulation, the solution domain which moves with the welding heat source was introduced to minimize the number of elements, and consequently the computation time of the three-dimensional program. Since the moving solution domain is small compared with the real weld structure, there are two kinds of boundaries, namely, solid metal-atmosphere boundary and solid metalsolid metal boundary. The heat loss through the solid metal-solid metal boundary was considered through a conduction heat flow and the heat flow through the solid metal-atmosphere boundary through a convection heat flow. As the solution domain moves with the progress of welding, new boundary conditions and new elements were generated in front of the heat source, while some elements disappeared in the rear of it. The initial temperature distribution of the new elements was determined by c...

Precharge system in a SRAM

Abstract: A precharge system of the divided bit line types for a SRAM (Static Random Access Memory) reduces the active current consumption and bit line peak current by decreasing the number of bit lines to be precharged at any one time during a precharge cycle. For this, the system has a block selection signal generator that responds to certain column addresses with a block selection signal. A sub-block selection signal generator responds to certain addresses among the remaining column addresses with a sub-block selection signal. A precharge decoder responds to pulses from the pulse generator and the block selection signal with a block selection precharge signal. A divided bit line precharge decoder responds to the sub-block selection signal and block selection precharge signal with a pulse for precharging only a certain sub-block of a certain block of the array of memory cells of the SRAM. A column predecoder responds to the block and sub-block selection signals with a block selecting pulse, and a column decoder responds to the block selecting pulse and the remaining column addresses to connect certain bit lines of the sub-block with a data line. The advantages of this are to reduce the power consumption of such a SRAM chip, and the noise in its power supply voltage, by precharging of only a portion of the whole number of bit lines at any one time.

Power feeding and input signal switching control system for video tape recorder combined with television receiver and camera in a body

Abstract: A power feeding and input signal switching control system for use in conjunction with a video tape recording and reproducing apparatus which includes a video tape recorder, a television receiver and a camera combined together in a body. Each power source for operating each device in the apparatus is selectively fed to only devices to be operated in response to a switching action in a controller and simultaneously an input source of video and audio signals to the video tape recorder is selectively switched by the same switching action in the controller.

Redundancy circuit for use in a semiconductor memory device

Abstract: A normal decoder and a redundant decoder having address program devices are used for the replacement of bad cells. The number of address program devices is one more than the number of input address bits for selecting a normal row or column. The input signals of the additional program device are complementary to the input signals of one of the other program devices. The program of the program devices have two steps to repair the faulty cells. To increase the reliability of redundancy, a nonvolatile memory element used in the program devices is a bridge connected four cell FLOTOX type nonvolatile memory device.

Method for fabricating a BiCMOS device

Abstract: This invention provides a method for fabricating a BiCMOS device, in which said device has a Si substrate of a first conductivity in which there is formed a first substrate region of a second conductivity for a bipolar transistor, a second substrate region of said second conductivity for a first MOSFET, having a source and drain of the first conductivity, and in which a part of said Si substrate is formed to provide a second MOSFET which has a source and drain of the second conductivity. A first nitride layer is used to prevent the substrate under a masking layer from oxidizing during the following oxidation processes, wherein the masking layer is composed of a oxide layer and the nitride layer. After some processes, the masking layer is removed. Implanting As impurities, a new oxide layer and a new nitride layer are deposited, wherein the role of the nitride layer is to protect a shallow emitter region. After that, a new clean oxide layer is grown for a gate insulator layer, and controllable clean gate oxide layer is obtained.

Circuit and method for power efficiency improvement of induction motors

Abstract: A circuit and method to improve power efficiency of AC induction motors is described for adopting an AC PWM chopper method in power input controls. For a period of several seconds after initially supplying power source voltage, the starting voltage is bypassed by a relay switch to prevent malfunctioning of devices. A PWM waveform is provided by a microcomputer and it is combined with a zero crossing signal of the power source voltage. The combined signal is controlled and buffered by photo couplers, by which power source voltage is controlled with transistors of a power controller unit. A current flow through the motor is detected and store into memory of the microcomputer. In a next sequence, another PWM waveform is provided to again detect other current flow through the motor and its detected value is compared with the previous value store in the memory. These sequences are repeated to search for a minimum current value according to variation of loading on the motor.

Laser drum for use in recording and reproducing information on optical tapes

Abstract: A laser drum which can optically record and reproduce information on optical tapes. The laser drum comprises an upper drum which has two projection holes, rotates and is fitted with semiconductor lasers, a total reflective prism, stoppers, diffraction gratings, beam splitters, object lenses, condensing lenses and photodetectors.

Sense amplifier optimized lay-out from dynamic random access memories on complementary metal oxide semicondutor

Abstract: A sense amplifier having an optimized structural lay-out for D-RAM on the C-MOS provides the same time lag from nodes of the sense amplifier and does not produce unbalances in the voltages. This allows the sense amplifier to uniformly distribute the parasitic capacitance of the bit lines used for the D-RAM on the C-MOS. The sense amplifier is connected to a memory cell array so that transistors and capacitors are coupled with a plurality of bit lines and word lines situated on the semiconductor substrate. The amplifier has a first semiconductor region which is within an N type well region located on the P type semiconductor substrate to form a first latch circuit. A second semiconductor region which is contiguous to the N type well region is also formed on the semiconductor substrate to form an N-MOS transistor. Lastly, a third semiconductor region, which is contiguous to the N type well region and the second semiconductor region, forms a second latch circuit having an N-MOS transistor. Thus, the sense amplifier is formed at a gate of the N-MOS transistor so that a transfer from the gate of N-MOS transistor through openings in the substrate caused by voltage differences produced by the charge distribution and storage capacitor of bit lines during an active cycle does not have a time lag.

Data transmission circuit having decreased parasitic capacitance

Abstract: A data transmission circuit for CMOS dynamic random access memory devices having a data input buffer for converting TTL input data signals to CMOS logic level data signals and providing true and complement data signals on a pair of data bus lines, a pair of transmission gates for transmitting the true and complement data signals to a pair of true and complement I/O bus lines comprising a pair of similar constitutional I/O bus line pull-up or pull-down circuits between the output lines of the transmission gates and the I/O bus lines for making logic operations on the data bus lines. The I/O bus lines alternate at the time of a writing operation and a I/O bus line equalizing circuit is connected between the true and complement I/O bus lines for equalizing the pair of the I/O bus lines at a high speed, before or after a writing cycle.

Multiple spiral inductors for DC biasing of an amplifier

Abstract: A monolithic semiconductor having an on-chip DC biasing including a plurality of series connected spiral inductors connected between the respective biasing and the semiconductor circuit. The spiral inductors provide a low resistive path for the DC biasing while also having a high inductance for isolating the RF signal from the bias sources, thereby improving the low frequency response. The capacitance associated with the individual spirals, however, is significantly less than the capacitance associated with a single spiral inductor having an equivalent inductance of the small series connected spirals; thus the higher frequency response is not degraded while the low frequency response has been improved.

Adaptive scanning line converting circuit for a television receiver

Abstract: A circuit and technique for using only a line memory that has small capacity and selecting a proper interpolation filter according to the correlationship of vertical and slanting directions between two scanning lines of input signals. This system performs the steps of applying interlaced scanning signals to an image signal delaying circuit having delaying elements, generating a plurality of signals according to each delay, filtering in a two dimensional space filter, detecting the correlationship of the vertical and slanting directions between the lines by logic operations of the delay signal, selecting a proper space filter of the two dimensional space filter in response to the detected signal and converting in time axis with the interlaced scanning signals and a signal properly generated through the interpolation filter of a filter selector, thereby economically obtaining a high quality picture image.

Adaptive-type luminance/color signal separation circuit using the horizontal and vertical correlation in television receiver

Abstract: The technique for separating luminance(Y)/color(C) signals in NTSC-type television TV receivers is disclosed. To decrease deterioration in picture quality due to inaccuracy of Y/C signal separation in color television receivers, comb filters have been used and a three-dimensional signal processing technique using a frame memory has recently been disclosed. To avoid a complicated constitution of circuit which consists in the necessity of large scale memory, this invention provides a Y/C signal separating circuit suitable for digitalization without increasing the complication of circuit by using a line memory. Also, horizontal and vertical peaking filters utilizing horizontal and vertical correlation of video signals in said separating process are provided to change the bandwidth of the filter according to signals, thereby improving in resolution and S/N ratio.

A method of semiconductor device isolation by lateral separation

Abstract: An oxide layer (21) is formed on a silicon substrate; a silicon-nitride layer (22) deposited as an oxidation mask, and an opening (24) formed by etching part of said silicon-nitride layer. A layer of polysilicon (25) is deposited on the surface of said silicon-nitride and on said opening after forming the opening. A polysilicon spacer (26) of suitable width is then formed in contact with the side walls of said opening through reactive ion etching without a mask; the polysilicon spacer region is oxidized through the formation of a field oxide after forming the polysilicon spacer. Finally the isolation region (28) is formed with a predetermined thickness of field oxide through etching the surface of the silicon-nitride and the oxide layers, after said oxidation process. The method reduces the generation of a crystal defects due to thermal stress and lateral encroachment ('bird's beak) into the active region.

Heat-exchanging member of a dehumidifier

Abstract: A heat-exchanging member of a dehumidifier designed and constructed for high-efficiency heat-exchanging is disclosed. The heat-exchanging member comprises two tubes which are united by a bridge having several openings thereon for efficient drainage of the waterdrops of condensate, and which are provided with a few projections for improving moisture-removing efficiency.

Computer video control system

Abstract: Video control circuitry for controlling the video format presented to the cathode ray tube or screen and capable of providing a combination of character generation and cell generation along with other video types of control. The video controller may comprise a video memory means for controlling writing into and reading therefrom and means defining both a memory address and a memory data. There is a video data bus coupled to the video memory means and a processor address bus. A cathode ray tube controller has address lines and the address lines are connected to multiplexer means for selecting either the controller address lines or the processor lines. Control means are provided for controlling the multiplexer means so that in one state thereof the video memory means is addressed from the cathode ray tube controller means and in the other state the video memory means is addressed from the central processing unit address. This occurs on an interleaved basis with the CRT clock basically operating at the normal refresh cycle rate. However, in accordance with the invention the CRT clock is essentially divided so that one half of the clock cycle is used for communication from the CPU to the video memory means. This provides for improved screen display.

Corner construction for joining angularly related members

Abstract: A corner construction fastening one cabinet plate member to another cabinet plate member by using a joining element, the cabinet plate members having a pair of inner and outer walls at both sides and the joining element having a body to support the walls and under sides of the members and two extensions to be inserted into slots formed in end portions of the walls.

A light emitting semi- conductor device having current overload protection

Abstract: This housing contains a radiator 17 integrated with a main base 40, a first pin 21, a second pin 20 insulated from the first and which projects inside the volume of the housing 19, and a cover 16 provided with a transparent glass window 24. According to the invention, this housing comprises: a second insulator-forming conduction region separated from a region for mounting the electroluminescent component on the substrate; a first resistor-forming conduction region made in the second region; a thin insulating film deposited on the insulator-forming region and the resistor-forming region; first and second openings for contact with the protective resistor, which are made by removing the insulating film only within a contact region of the resistor-forming region; a metal-plated reverse face 7 of an auxiliary silicon chip, connected to the radiator material 17; an electroluminescent component 15 fixed on the region for mounting the auxiliary silicon chip; and first and second pins connected respectively, by a soldered wire, to the first and second contact openings of the protection resistor.

Level shifter for an input/output bus in a CMOS dynamic ram

Abstract: A level shifter for an input/output bus in a CMOS dynamic RAM employs a first and second PMOS transistor. The first and second PMOS transistors are connected to and cut off a current flow between a pair of input/output lines and a pair of input/output sense amplifier input lines which are connected to input/output sense amplifiers. First and second inverters are included for each of the first and second PMOS transistors, each inverter has an input for receiving a signal for a selection of the input/output line pair and has a respective output which is connected to a corresponding gate and drain of the first and second PMOS transistors.

Junction-breakdown protection semiconductor device

Abstract: A junction-breakdown protection semiconductor device provides a well region which prevents the junction between a metal conductor and a diffused region from breakdown even under a high voltage or high current input. The junction-breakdown protection semiconductor device includes a metal conductor to which a high voltage is applied a semiconductor region of high impurity concentration having a conductivity type which is opposite to the conductivity type of the substrate is connected to the metal conductor through an opening in an insulating film. A second semiconductor region of the same conductivity type as the first semiconductor region is formed deeper in junction depth than the first semiconductor region under the opening in the insulator for ohmic connection on the surface of the first semiconductor region. This invention has the advantage of increased margin even with a alignment error of the ohmic connection in the fabricating process and thus provides an increased reliability of the semiconductor device.

Single driving system for tape loading and reel mode conversion of VCR

Abstract: A single driving system for both tape loading and operational mode conversion of video cassette recorder is disclosed. The system comprises a single drive motor, a drive gear and a selective power transmission system which are engaged successively and made to be used in a VCR provided with conventional tape loading ring gear and reel mode converting means. The selective power transmission device may comprise a sun gear, one or two planet gears, a gear for tape loading movement, a gear for reel mode converting movement and a means to control and select the movement of latter two gears.

Fin attachment for microwave oven dispersing fans

Abstract: A supplementary fin for attachment to the blades of dispersion fans in microwave ovens is disclosed. Supplementary fins 7 and 7a are removably attached to the underside of respective blades 2 and 2a of standard dispersing fan 1. To maintain balance of the fan assembly, supplementary fins 7b and 7c are attached to the top side of respective dispersing fan blades 2b and 2c. The removable attachment capability of the supplementary fins is accomplished by sliding of tongue 5 through a rectangular hole 4 so as to align a fixing hole 6 with a circular hole 3. An expandable clip 9 is inserted through holes 3 and 6 and is expanded by insertion of a pin 8 so as to removably attach the supplementary fin 7 to dispersing fan blade 2. This removable attachment capability allows optimum dispersion characteristics to be achieved for a variety of dispersing fans, fan motors, and oven air venting configurations, by simple replacement of supplementary fins with supplementary fins of different design.

Grating adjustment apparatus of 3-beam type optical pick-up

Abstract: This invention relates to a grating adjustment apparatus of 3-beam type optical pick-up for the compact disk player and, more particularly, to an apparatus automatically and readily adjusting a grating to the angle where the target value of a tracking error signal is obtainable Sub-beam currents from the optical pick-up is, through current-voltage transducing amplifiers, converted into voltage signals, which are applied to a differential amplifier The differential amplifier puts out the tracking error signal mixed with noise, which passes through a band pass filter removing said noise So only pure tracking error signal is obtained, which is, after its phase is compensated by the low frequency lag compensator, applied to a differentiator This signal is applied to a discriminator When the tracking error signal detected by the discriminator is far smaller than the lowest limit of the target value of the grating adjustment, a jig actuator regulates the grating angle in the direction that said signal can be increased, by rotating a motor In the end, the target value of the tracking error signal is obtainable When the tracking error signal detected by the discriminator is larger than the target value, a system controller generates an amplifier enable signal making the discriminator produce a grating adjustment stop signal and a tuned indicating signal, whereby the motor driving stage generates a signal for braking the motor In the end, the target value of the tracking error signal is maintainable

Video tape recorder system

Abstract: A tape format of 4-mm wide video tape for use in a video tape recorder adopting helical scanning and azimuth recording methods is disclosed in conjunction with a video tape recorder system thereof, which enables the video tape recorder to achieve the greatest size-reduction and improve the resolution in picture reproducing by raising the S/N ratio of video signals. The tape format includes a video width area for an automatic track finding signal to control the traveling of tape and the video signal consisting of color signals and luminance signals, an option track area for recording audio signals, a first guide area for keeping the minimum part of tape in touch with the upper drum, a second guide area for separating the audio signals of the option track area from the video signals of the video width area, and first and second overlap areas respectively below the first guide area and above the second guide area, provided for overlapping the video signals on the edges of video tracks in recording operation.

Apparatus for quick starting tape in video cassette recorders

Abstract: An apparatus for quick starting of tape forwarding-and-rewinding operation for video cassette recorders, wherein fast-forwarding or rewinding operation of a video tape can be quickly started, because loading plates, which are locked in loading holes as during the recording or reproducing operation, keep the tape being loaded on a head drum, while the tape can be wound by only the driving force to rotate one of the reel discs, because two guide grooves in different shapes are provided on upper and lower surfaces of a cam gear and so a tension pole and a pinch roller come off the tape and the tape gets out of touch with various fixed posts in its travelling route, before the fast-forwarding or rewinding operation is started.

Image processing method

Abstract: PURPOSE: To realize the expression of a creative image by adding the error between data on the single picture element of an original image and data on the single picture element processed within plural picture elements to the data on the single picture element of the original image and converting successively these data into plural picture elements. CONSTITUTION: The R, G and B data of an original image are defined as X=(x, y, 1)=70, X=(x, y, 2)=140 and X=(x, y, 3)=180 respectively together with a color number i=3(50, 100, 200). Then the first picture element of output data is equal to the color number data (50, 100, 200) nearest original image data (70, 140, 180) and therefore the arithmetic contents a decided as the value (50, 100, 200). Here the error values of the original image data are set at +20, -40 and +20 for R, G and B respectively. In this respect, these error values are taken into consideration when the next output is obtained. Then 20 is added to 70 of R of the original image data since R is short by 20 and the color number data closest to the value of said R is extracted. The similar processing is carried out with G and B respectively. This arithmetic is repeated by the frequency equal to (2×2) picture elements. As a result, the original image can be expressed in a comparatively small number of errors. COPYRIGHT: (C)1988,JPO&Japio