Showing papers by "STMicroelectronics published in 1983"

Repairable ROM array

Abstract: The individual rows of a ROM array are accessed by a row decoder/driver in response to the arrival of the address of the individual row on the address lines. A plurality of programmable switches store the address of a row of ROM array found to contain one or more defects. If the incoming address is that of the defective row each of a plurality of comparators connected to both an address line and the associated switch outputs a coincidence signal to an AND gate. The output of the AND gate accesses a spare row of RAM which thus replaces the defective row of the ROM array. Access to the spare row is automatic upon receipt of the address of the defective row. Each column of the ROM array contains a check bit computed from the remaining contents of the respective column, and the data to be stored in the spare row is generated from the remaining contents of the ROM array. At initialization, the generated data which should have been stored in the defective row is written into the spare row.

Functional command for semiconductor memory

Abstract: A method and apparatus is described for initiating a selected functional mode for a semiconductor memory circuit The memory circuit typically operates by receiving a plurality of defined operational signals which control data transfer to and from the memory circuit The method for initiating the selected functional mode comprises applying an active state of at least a first of the operational signals to the memory circuit followed by applying an active state of a second of the operational signals to the memory circuit The timing of the second operational signal relative to the first operational signal is not within the defined specification limits of the first and the second operational signals for conventional data transfer to and from the memory The step of applying the active state of the second operational signal, outside the defined limits, serves to initiate the selected functional mode for the memory circuit An example of the selected functional mode is the activation of circuitry (62) which serves to apply a predetermined data state to a redundant column (63) which can be substituted to replace a defective primary column within a memory array After the memory array has previously received a first data state and the circuit (62) is activated to apply a second data state to the redundant column (63) the memory array is read and each column which produces a second data state is determined to be a redundant column With knowledge of the column substitution algorithm, it can then be determined which of the redundant columns have been programmed to replace specific original columns This method can therefore determine the physical configuration of the memory circuit despite the incorporation of redundant elements into the primary memory array

High density ROM in separate isolation well on single with chip

Abstract: A programmable, high speed, single chip microcomputer includes 4K of RAM, ROM, registers and an ALU. Program can be stored in the on-chip RAM. The first local variable of each process to be executed is a workspace pointer (WPTR), and each process has a respective workspace identified by its WPTR. For each process, addressing of other variables is relative to the current WPTR, which is stored in a workpiece pointer register (WPTR REG). Instructions are constant bit size, having a function portion and a data portion loaded, respectively, into an instruction buffer (IB) and an operand register (OREGTR). Memory address locations are formed by combining the contents of the workspace pointer register and the operand register, or the contents of the A Register and the operand register. A set of "direct functions" obtains data from OREG. "Indirect functions" use the OREG contents to identify other functions, obtaining data from registers other than the operand register. A "prefixing" function (PFIX) develops operands having long bit lengths. Scheduling and descheduling of processes are achieved by forming a linked list within the several workspaces for the active processes. Each workspace identifies the workspace pointer of the next process to be executed. Each workspace contains in memory the identification of the next instruction to be executed for that respective process. A "last pointer" register (LPTR REG.) cooperates in the scheduling operations. Each microcomputer chip can be coupled serially to other such chips on a respective pair of only two wires, each a unidirectional channel. Each channel also has two registers, one for process identification and one for data. Communications are synchronized.