Showing papers by "STMicroelectronics published in 1985"

Manipulation and handling of integrated circuit dice

Abstract: A method and apparatus for automated handling of integrated circuit dice (7-55). One apparatus (13-120) provides for transfer or randomly oriented dice within oversized receptacles (7-225) to precision alignment devices (13-225) and, subsequently, provides transfer from the precisely aligned positions to a further set of receptacles (9-225). Further, apparatus is used to rotate a chip carrier by 180 degrees to invert and transfer dice from one set of receptacles to another.

Method of fabrication of aluminum contacts through a thick insulating layer in an integrated circuit

Abstract: In order to form aluminum interconnections through a thick insulating layer in an integrated circuit without any attendant danger of rupture at the level of the contact openings in the insulating layer between the interconnection layer and the substrate, the contact openings are first filled with polycrystalline silicon or a metal having high covering power and deposited by chemical decomposition in gas phase, whereupon the aluminum is deposited by vacuum evaporation.

Chip selection in automatic assembly of integrated circuit

Abstract: An apparatus (7-100) for removing selected integrated circuit dice from a wafer array of dice sequentially moves a striker (7-114) above a tape (420) to the underside of which the array is mounted and then knocks a die down from the array of dice into a receptacle (7-228) for transport to further processing stages. The apparatus thus provides an automatic method of removing dice selectively from a wafer using stored data.

Process for the fabrication of a nonvolatile memory cell with very small thin oxide area and cell

Abstract: On the doped area of a monocrystalline silicon substrate is grown a thick oxide layer a side portion of which is subjected to etching and underetching within a predetermined area until it uncovers an edge of silicon on which is then grown thin oxide; polycrystalline silicon layers separated by an oxide layer are then deposited to produce a nonvolatile memory cell in which the floating gate consisting of one of said polycrystalline silicon layers is separated from the underlying doped area of the substrate, which constitutes the drain, by a very small thin oxide area which adjoins an extended area of thick oxide. The electrical capacitance between the floating gate and the drain is thus reduced with resulting smaller dimensions of the cell for given performance.

Method for DMOS semiconductor device fabrication

Abstract: An improved method for the fabrication of a DMOS transistor. The method comprises forming the source region of the transistor by introducing doping from a doped, thin polycrystalline layer. A thin insulating layer is used to protect the body channel contact region from the source doping, and the thin polycrystalline layer is completely consumed and converted into an insulator by oxidation subsequent to the source doping step.

Audio amplifier switch-on control circuit

Abstract: A capacitor which is progressively chargeable in response to a switching on of the equipment, however brought about, is associated with an oscillating circuit with intervention threshold. As the load voltage of said capacitor increases the oscillating circuit shifts from a first to a second operating state, generating a switch-on current for the audio amplifier. The latter can be placed in stand-by condition by discharging to earth said capacitor by means of a suitable switch.

Marker attachment for railroad equipment

Abstract: An improved attaching device is provided for securely mounting railroad signalling and monitoring equipment (10, 12) on the coupler (36) of a railroad car. A package including a supporting frame (22) to which the equipment is fastened by a draw pull (16) rests on the top surface of the coupler. The supporting frame includes a mounting bracket (32) having an integral rod (50) which extends through the flag hole in the coupler knuckle. The end of the rod projects beyond the bottom of the coupler so that it can be secured. In the second embodiment (FIGS. 8 and 9), the rod (111) has bifurcated extensions (116, 118) which serve to strengthen the supporting frame (80). This embodiment also includes shock absorbing elements (108, 110 and 122). In a third embodiment, a post (162) slidably carries a shaft or rod (188) that is retractable into a locking position with the coupler. A crank (176) is used to retract the shaft into a locking position. The crank carries a locking bar (234) which cooperates with locking members (230, 232) on the equipment package to secure the package in place. The three embodiments all feature top of coupler mounting in such manner that the railroad signalling and monitoring equipment is not damaged in the event that another coupler engages the coupler on which the package is mounted.

Method of producing integrated circuits on an isolating substrate

Abstract: 1. A process for the manufacture of integrated circuits on an insulating substrate, consisting of forming a monocrystalline semiconductor layer on an insulating monocrystalline substrate, said layer being of a material with a crystalline structure sufficiently similar to that of the insulating substrate, with the aid of the following steps : (a) forming a fine layer of silicon oxide (12) on the insulating substrate (10), (b) engraving this oxide in accordance with a design of individual islands (14), (c) forming a monocrystalline semiconductor layer (18) at a high temperature from monocrystalline nuclei constituted by the zones (16) of the substrate formed under the islands (14), and (d) engraving the semiconductor layer (18) with a design essentially the same as the engraved design of the silicon oxide.

CMOS output buffer

Abstract: A synchronizing buffer arrangement for a CMOS memory with output drive transistors (21 and 22) receiving one of a pair of input data signals (from 11 and 12 respectively), and being subject to the pull-up and pull-down support of the other of said data signals (from 11' and 12').

Access neutralization device to protect an integrated-circuit zone

Abstract: L'invention a pour objet un dispositif de neutralisation de l'acces (4) a une zone (2) a proteger d'un circuit integre. The invention relates to an access neutralization device (4) to an area (2) to be protected of an integrated circuit. Dans ce dispositif une partie fusible (6) assurant la liaison entre une borne d'acces (5) et une zone (2) a proteger d'un circuit integre et reliee, par son extremite (8) la plus proche de la zone a proteger, a une jonction (9) obtenue a l'intersection d'une couche (7) dont le type de conductivite est l'inverse (N+) du type de conductivite (P) dans lequel est realise le substrat (1) du circuit integre. In this device a fusible part (6) ensuring the connection between an access terminal (5) and a zone (2) to be protected of an integrated and connected circuit, by its end (8) closest to the area to protected, to a junction (9) obtained at the intersection of a layer (7) whose conductivity type is the inverse (N +) of the conductivity type (P) in which is formed the substrate (1) of the circuit integrated. En utilisation normale du circuit cette jonction est polarisee en inverse. In normal use of the circuit junction that is reverse biased. Elle n'est alimentee en direct qu'au moment ou l'on veut faire fondre le fusible. It is powered directly only when we want to melt the fuse. Ceci rend irreversiblement inaccessible la zone a proteger du circuit integre. This makes irreversibly unreachable area to protect the integrated circuit. Application: cartes a memoire. Application: memory cards.

Error-correcting circuit having a reduced syndrome word

Abstract: An error-correction circuit for correcting up to one error in an M-bit data field having the conventional number K parity bits associated with it uses a syndrome word having K-1 bits. The data elements are ordered sequentially and the K-1 bit syndrome word points to errors in the data only, not to errors in the parity bits. One of the data addresses in the field is reserved as a no-error flag and a Kth parity check bit associated with the syndrome word flags an error in the parity bits.

Method for producing a DMOS semiconductor device

Abstract: An improved method for the fabrication of a DMOS transistor. The method comprises forming the source region of the transistor by introducing doping from a doped, thin polycrystalline layer. A thin insulating layer is used to protect the body channel contact region, from the source doping, and the thin polycrystalline layer is completely consumed and converted into an insulator by oxidation subsequent to the source doping step.

CMOS ROM Data select circuit

Abstract: © A data select circuit for selecting a column line in a CMOS ROM and for establishing a connection between a pair of bit lines and corresponding data lines uses a single NMOS pull-down transistor on the column line and a pair of P-channel pass transistors on the bit lines, the pass transistor gates being controlled not by an inverted column decode line, but by the column line itself, thus reducing the capaca- tive load on the column decoder and saving space.

High-speed parity check circuit

Abstract: A high speed parity circuit uses a sequence of simplified exclusive-OR circuits responsive to data input terminals containing a data signal and its complement and terminating in a sense amplifier, together with an operating sequence in which the inputs to the sequence are grounded while the data lines are first brought high and then set to the correct data state to form a pair of separate paths through the sequence when no current flows, after which set-up operation an input voltage circuit raises the voltage on one of the paths smoothly, so that the sense amplifier can respond as soon as its input is large enough, without waiting for a settling time.

Electrically erasable and reprogrammable memory point comprising a floating gate above a control gate

Abstract: 1. A memory point of the floating gate transistor type in which the floating gate transistor comprises a source zone (32, 34) (of N-type), a drain zone (28, 30) (of N-type), a channel zone (36, 38, 40) (of P-type), a control gate (42), a floating gate (48) covering the channel zone and separated from the latter and from the control gate by thin insulating layers (50, 52), and finally an injection zone (58) in which the floating gate is separated from the substrate only by a very thin insulating layer (56), in which, above the channel zone, the floating gate (48) extends over the control gate (42) except for a portion (40) of the length of the channel, portion in which the channel is covered over its entire width only by the floating gate, characterized in that the injection zone, covered by said very thin insulating layer (56) and by the floating gate (48), is a semiconductor zone (58) of N**- -type and of a low doping rate, this zone being delimited, substantially above at least one edge of the floating gate situated above this injection zone, by a zone of N**+ -type and of a high doping rate (60).

Integrated triac structure with diac control

Abstract: An integrated triac structure with diac control is provided on a common substrate. The diac is connected to the gate of the triac by a common metallization on the integrated substrate. The diac has a lateral structure with two metallizations on the same face of the substrate. It is separated from the triac by a passivated furrow 16 deeper than the gate region of the triac.

Process for the fabrication of a nonvolatile memory cell with very small thin oxide area and cell obtained by said process

Abstract: On the doped area (7) of a monocrystalline silicium substrate (1) is grown a thick oxide layer (8) a side portion of which is subjected to etching and underetching within a predetermined area until it uncovers an edge of silicium (12) on which is then grown thin oxide (13); polycrystalline silicium layers (14, 16) separated by an oxide layer (15) are then deposited to produce a nonvolatile memory cell in which the floating gate consisting of one (14) of said polycrystalline silicium of one (14) of said polycristalline silicium layers is separated from the underlying doped area (7) of the substrate, which constitutes the drain, by a very small thin oxide area (13) which adjoins an extended area of thick oxide (8). The electrical capacitance between the floating gate (14) and the drain (7) is thus reduced with resulting smaller dimensions of the cell for given performance.

Robot gripper for integrated circuit leadframes.

Abstract: A gripping mechanism adapted for picking up thin, flexible, perforated sheets employs a set of claws (8-20) together with a planar member (8-22) to define a volume for enclosing the sheet. Thus the problems of handling damage to the fragile sheets are solved.

Drive circuit for a deflection power transistor

Abstract: Die Erfindung betrifft eine Ansteuerschaltung fur einen Leistungstransistor, der sich in einer Ablenkschaltung eines Fernsehgerats befindet und eine Ablenkwicklung mit einem rampenformig ansteigenden Ablenkstrom versorgt The invention relates to a driving circuit for a power transistor which is located in a deflection circuit of a television set and supplies a deflection winding with an upramping deflection current Die Ansteuerschaltung wird periodisch mit Einschaltimpulsen einer der Rampenlange des Ablekstroms entsprechenden Dauer gespeist The drive circuit is periodically fed with switching-on of one of the ramp length of the Ablekstroms corresponding duration Sie beaufschlagt den Leistungstransistor wahrend der Einschaltimpulsdauer mit einem ansteigenden Einschaltbasisstrom, der den Leistungstransistor wahrend im wesentlichen der gesamten Einschaltimpulsdauer in den Sattisgungszustand steuert It acts on the power transistor during the switching-on with a rising Einschaltimpulsdauer which controls the power transistor during substantially the entire Einschaltimpulsdauer in the Sattisgungszustand Nach Beendigung des Einschaltimpulses steuert die Ansteuerschaltung einen im Verhaltnis zum Anstieg des Einschaltbasisstroms rasch abnehmenden und schlieslich die Polaritat wechselnden Abschaltbasisstrom, der eine schnelle Ruckfuhrung des Leistungstransistors aus dem Sattigungs- in den Sperrzustand bewirkt After completion of the switch-on pulse, the drive circuit controls a rapidly decreasing in proportion to the increase of the Einschaltbasisstroms and finally the polarity changing Abschaltbasisstrom, which causes a rapid return of the power transistor from the saturation in the locked state Dem Leistungstransistor ist eine Sensorvorrichtung zugeordnet, die der Ansteueurschaltung ein dem Momentanwert des Transistorhaupstroms proportionales Istwertsignal liefert The power transistor is assigned a sensor device which provides the Ansteueurschaltung proportional to the instantaneous value of the Transistorhaupstroms feedback signal Die Ansteuerschaltung regelt den Einschaltbasisstrom wahrend seines gesamten Anstiegs in Abhangigkeit von dem Istwertsignal auf einen Wert, der den Leistungstransistor mit nur geringer Ubersteuerung in dem gesattigten Zustand halt The drive circuit controls the switching-on throughout its rise in response to the feedback signal to a value which maintains the power transistor with little clipping in the saturated state Die Ansteuerschaltung steuert die Steilheit des Abschaltbasisstroms proportional zu dem am Ende des Einschaltimpulses auftretenden Istwertsignal The drive circuit controls the steepness of the Abschaltbasisstroms proportional to the occurring at the end of the switch-feedback signal

Method of manufacturing aluminium contacts through a thick insulating layer in a circuit

Abstract: L'invention concerne les circuits integres. The invention relates to integrated circuits. Pour realiser des interconnexions en aluminium (14) sans risque de cassure au niveau des ouvertures de contact dans la couche isolante (12) separant la couche d'interconnexion (14) du substrat (10), on propose de combler d'abord ces ouvertures avec du silicium polycristallin (18) ou un metal a fort pouvoir couvrant, depose par decomposition chimique en phase vapeur. For making aluminum interconnections (14) without risk of breakage at the contact openings in the insulating layer (12) separating the interconnect layer (14) of the substrate (10), it is proposed to first fill these openings with polycrystalline silicon (18) or a high covering power metal, deposited by chemical vapor phase. Apres quoi, on depose l'aluminium (14) par evaporation. Thereafter, depositing aluminum (14) by evaporation.

Structure integree de triac a commande par diac

Abstract: L'invention concerne les triacs commandes par un diac. On realise sur un substrat commun l'integration d'un triac et d'un diac. Le diac est connecte a la gâchette du triac par une metallisation commune (14, 46) sur le substrat integre. Le diac a une structure laterale avec deux metallisations (44, 46) sur la meme face du substrat. IIest separe du triac par un sillon passive 16 plus profond que la region de gachette (23) du triac.

Procédé de réalisation de contacts d'aluminium à travers une couche isolante épaisse dans un circuit intégré

Abstract: L'invention concerne les circuits integres. Pour realiser des interconnexions en aluminium (14) sans risque de cassure au niveau des ouvertures de contact dans la couche isolante (12) separant la couche d'interconnexion (14) du substrat (10), on propose de combler d'abord ces ouvertures avec du silicium polycristallin (18) ou un metal a fort pouvoir couvrant, depose par decomposition chimique en phase vapeur. Apres quoi, on depose l'aluminium (14) par evaporation.

Microprocessor with a stop function of the event counter.

Abstract: 1. A microprocessor comprising a built-in event counter (16) and having a mode selection terminal (MDS) indicating, when it is activated, that the microprocessor should be put in one mode selected from several, and a register of the selected mode (14) retaining in its memory information about the mode which was selected during activation of the mode selection terminal, one of the possible modes being a non-user mode which is employed during the checking of application programs of the microprocessor, characterized in that it comprises a logic circuit (18) which establishes a command for stopping the event counter when the following combination of states exists : - the microprocessor is not in the reinitialization phase, - the mode selection terminal is activated, - the mode selection register indicates that a mode or a group of modes, including a non-user mode, has been selected.

Redresseur monoalternance a capacites commutees

Abstract: L'INVENTION CONCERNE LES CIRCUITS INTEGRES A CAPACITES COMMUTEES. IL EST DECRIT UN CIRCUIT AYANT UNE FONCTION DE REDRESSEMENT MONOALTERNANCE FONCTIONNANT DE MANIERE ECHANTILLONNEE COMPORTANT UN AMPLIFICATEUR OPERATIONNEL AO, DES INTERRUPTEURS I1 A I6 ACTIONNES SELON DEUX PHASES DE FERMETURE DISJOINTES A ET B, DEUX TRANSISTORS T1 ET T2 AYANT LEUR GRILLE RELIEE A LEUR DRAIN, ET TROIS CAPACITES C1, C2, C3, LES ALTERNANCES NON SUPPRIMEES (POSITIVES OU NEGATIVES) APPARAISSANT AUX BORNES DE C3. CE REDRESSEUR ELIMINE L'INFLUENCE DE LA TENSION DE DECALAGE A L'ENTREE DE L'AMPLIFICATEUR AO.

Bipolar microwave integratable transistor and method therefor

Abstract: A method of fabricating bipolar integratable transistors includes a recrystallization step. A monocrystalline epitaxiaf layer is deposed upon a highly doped substrate and impurities are introduced into a portion of the epitaxial layer to form a first transistor region. A polysilicon layer is deposed upon the surface and a portion of the polycrystalline layer is recrystaf- lized wherein the first transistor region serves as a seed. Impurities are introduced into the recrystallized portion to form a base. An additional polysilicon layer is deposed over the substrate and a portion is recrystallized wherein the base serves as a seed. A second transistor region is formed in the recrystallized portion of the additional polysilicon layer.

Integrated structure of a triac controlled by a diac

Abstract: The invention relates to triacs controlled by a diac. The integration of a triac and a diac is carried out on a common substrate. The diac is connected to the triac trigger by a common metallization (14, 46) on the integrated substrate. The diac has a lateral structure with two metallizations (44, 46) on the same face of the substrate. It is separated from the triac by a passivated groove 16 deeper than the trigger region (23) of the triac.

Interdigitated bit line rom

Abstract: An integrated circuit memory employs a set of interdigitated bit and column lines containing multiple sets of data fields in which selection of a column line causes data signals to appear on both left and right adjacent bit lines and in which a selection circuit discards one of each pair of data signals, so that the memory elements containing the data are physically spread apart and also that a greater number of columns must be selected to provide a given amount of output data.

Impedance-matched leads.

Abstract: An integrated-circuit leadframe employs individual leads (5-120) that are formed from a layer of dielectric (10-6) laminated between two conductors (10-2, 10-4) and shaped to have a specified impedance matched to the impedance of a socket for the leads (5-120) and terminated at the top of an integrated circuit with a resistor having the impedance value.