Showing papers by "Yeshwantrao Chavan College of Engineering published in 2005"
01 Nov 2005
TL;DR: A ternary ADC using multi-valued logic levels of 0, 1 and 2 is developed and P-Spice simulation results of 3-digit circuits are presented.
Abstract: A ternary ADC using multi-valued logic levels of 0, 1 and 2 is developed. Properties of uni-polar ternary windows are modified to suit asynchronous conversion of bipolar signals. Two algorithms are presented, one giving a straight ternary code uses identical digit cell topologies while the other gives an additional offset ternary code. P-Spice simulation results of 3-digit circuits are presented.
1 citations
01 Jan 2005
TL;DR: The algorithm for SAR for successive approximation register (SAR) type analog to digital converter is developed for asynchronous design and the circuit is simulated on Spice for correctness of the approach.
Abstract: Asynchronous analog to digital converters (ADC) are normally flash type converters. Asynchronous design approach is proposed in this paper. Normally in design methodology for ADCs, either only flash approach is used or else the signals are sequentially processed. Advantages of asynchronous design are studied for successive approximation register (SAR) type analog to digital converter. The algorithm for SAR is developed for asynchronous design. The circuit is simulated on Spice for correctness of the approach. After successful results, the digital circuit is implemented in complex programmable logic device (CPLD) and other components such as digital to analog converter (DAC) and comparators etc. are used from available integrated circuits. The results obtained are presented and are favourable to expected performance.
1 citations