Showing papers by "Zoran Corporation published in 1986"

Electronically programmable gate array having programmable interconnect lines

Abstract: An electronically programmable gate array comprises a plurality of rows of logic cells with each cell having a plurality of inputs, at least one output, and a plurality of electronically programmable voltage levels for configuring the cell. A plurality of sets of interconnect lines are formed in the array with one set of interconnect lines provided between adjacent rows of logic cells with electronically programmable contacts connecting inputs and an output of each cell in a row of cells with two adjacent sets of interconnect lines. Each row of logic cells preferably includes alternating three-input cells and two-input cells. Each electronically programmable voltage level comprises two voltage alterable resistors serially connected between first and second voltage potentials. Each electronically programmable interconnect comprises a voltage alterable resistor.

Apparatus for addressing memory with data word and data block reversal capability

Abstract: Memory address generation circuitry includes two binary counters for generating addresses for application to an address bus. The least significant bits of one counter are connected to the address bus in bit positions corresponding to the most significant bits of the other counter whereby the two counters increment addresses in opposite directions. The mode of address generation permits addresses for data in normal order, data within data blocks in normal order and data blocks in reverse-bit order, and data within data blocks in bit-reverse order and data blocks in normal order. The circuitry has particular applicability in memory address generation when operating on data with algorithms for FFT operations in one or more dimensions.

Method of selectively making contact structures both with barrier metal and without barrier metal in a single process flow

Abstract: A semiconductor structure with ohmic contacts and variable resistance contacts has an interconnection pattern to the contacts including a first barrier metal in contact with the variable resistance contacts and a second metal contacting the barrier metal and the ohmic contacts. The barrier layer protects the amorphotized crystalline structure of the variable resistance contacts. Fabrication processes are described.

Cascadable digital filter processor employing moving coefficients

Abstract: A digital filter processor employs four multiplier-accumulator cells and an output accumulator for receiving and accumulating all cell outputs. Data is provided to all cells in parallel, and finite impulse coefficients are applied serially to all cells. A plurality of registers and at least one multiplexer interconnect the cells for transmitting the coefficients between cells. The registers can be employed for sample rate reduction or decimation. A plurality of processors can be cascaded for processing an increased number of coefficients without a reduction in sample time. Alternatively, data can be recycled in a processor to accommodate a number of coefficients greater than the number of cells at a reduced sampled sample rate. A cell address is provided for selecting cell outputs during the reading of the filtered/processed data.