Showing papers by "Zoran Corporation published in 1988"

Double layer voltage-programmable device and method of manufacturing same

Abstract: A voltage-programmable device in which the programming voltage Vp and the "off" resistance Ri are separately controlled. The device includes a body of semiconductor material having a doped region therein, and an amorphized layer in the doped region and abutting a surface, and a surface layer in the amorphized layer with the surface layer having a resistivity higher than the resistivity of the amorphized layer prior ot programming of the device. The surface layer has a miniscule thickness (on the order of 50-150 Angstroms) and does not affect the programming of the device. Moreover, the final resistance of the programmed device is not significantly affected by the presence of the first layer. The amorphized layer is formed by ion implantation, and the or by oxygen plasma treatment.

Method of fabricating electrically-programmable element in a semiconductor integrated circuit using a doped plug to extend the depth of a doped region

Abstract: An electrically programmable element is fabricated in a P-N junction isolated region of a semiconductor body by first extending the depth of the region in the body by introducing dopants through the region into the body by ion implantation or by diffusion and drive-in, and thereafter forming an amorphotized layer in the first region overlying the extended portion. The increased depth of the first region provided by the second region prevents damage to the P-N junction between the semiconductor body and the first region during formation of the amorphotized layer.

System Applications Of A New 32-Bit Floating-point DSP Processor

Abstract: Embodiment of DSP tasks requires an optimal blend of reg- ularly structured array processing and scalar oriented decisions making. The ZR34325 represents the first full IEEE floating- point integrated array processor on silicon, supplemented with the pertinent scalar and control flow capabilities. In order to meet the stringent processing requirements, found today in modern signal and image processing applications, the ZR34325 directly executes embedded DSP and array processing primitives on multidiniensional arrays. Furthermore, an integrated development environment which includes system software simulator, vectorized and parametric DSP, arithmetic and matrix library, C based assembler/linker and hardware development tools, facilitates top-down complete application development . To achieve performance bounds higher than plausible by a single device (45 MFLOPs peak), one must resort to a Multi- Processor Multi-Tasking (MPMT) schemes. The ZR34325 en- ables very efficient MPMT schemes for tasks where: (i) Execution- time is data independent (e.g. FFT); or (ii) Execution-time is data dependent (e.g. SVD algorithm).

Computation apparatus and method.

Abstract: A pipeline dprocessing computation apparatus for performing the Butterfly operation on complex data (A, B) as weighted by a complex factor (W) in accordance with the equations X = A + WB Y = A - WB in which partial products for subsequent data (A1, B1) weighted by a factor (W1) are obtained while the sum and difference of A and WB are obtained. In a preferred embodiment the total operation for one set of data is eleven clock cycles, and three sets of data can be operated on concurrently whereby two inputs are provided and two outputs obtained every four cycles.