EPG-sim is a newly-developed set of tools that performs execution-driven critical path simulation, trace generation, and simulation for serial, optimistically parallelized, and parallel application codes. These capabilities are integrated within a single framework through the use of intelligent source-level instrumentation. The ability to perform execution-driven simulations driven by optimistically parallelized codes, the ability to execute these simulations on parallel hosts, the use of source-level instrumentation, and the integration of the capabilities provided by EPG-sim are among the novel contributions of this work. EPG-sim has important uses in studying parallel architectures, parallelizing compilers, and parallel applications.

background

A Testbed for Studying Parallel Programs and Parallel Execution Architectures

Execution-driven tools for parallel simulation of parallel architectures and applications

Visual parallel programming and determinacy: a language specification, an analysis technique, and a programming tool

Collaborative editing systems support groups of people editing a document together over the computer network. People may work simultaneously on the same document, simultaneously on different copies of the document, or at different times on the original or copied document. The document types include text, diagrams, more complicated graphic objects, images, CAD drawings, multimedia, etc.. Collaborative editing research addresses many fundamental and challenging issues facing the designers of real-time groupware systems in general.

Third annual collaborative editing workshop

This dissertation considers the use of data prefetching and an alternative mechanism, data forwarding, for reducing memory latency due to interprocessor communication in cache coherent, shared memory multiprocessors The benefits of prefetching and forwarding are considered for large, numerical application codes with loop-level and vector parallelism Data prefetching is applied to these applications using two different multiprocessor prefetching algorithms implemented within a parallelizing compiler Data forwarding considers array references involved in communication-related accesses between successive parallel loops, rather than within a single loop nest A hybrid prefetching and forwarding scheme and a compiler algorithm for data forwarding are also presented
EPG-sim, a system of execution-driven simulation tools for studying parallel architectures, algorithms, and applications, was developed as a prerequisite for this work EPG-sim performs execution-driven simulation and critical path simulation within a single, integrated environment EPG-sim provides an extremely wide range of cost/accuracy trade-offs and a number of novel features compared to existing execution-driven systems The parallelism and communication behavior of numerical application codes are studied via EPG-sim critical path simulation, which establishes the potential performance of prefetching and forwarding for these codes The evaluation of prefetching and forwarding is accomplished via detailed EPG-sim execution-driven simulations of optimized, parallel versions of these application codes
Two multiprocessor prefetching algorithms are presented and compared A simple blocked vector prefetching algorithm, considerably less complex than existing software pipelined prefetching algorithms, is shown to be effective in reducing memory latency and increasing performance A Forwarding Write operation is used to evaluate the effectiveness of forwarding Data forwarding results in significant performance improvements over data prefetching for codes exhibiting less spatial locality A new hybrid prefetching and forwarding scheme is presented that provides increased performance stability by adapting to varying application characteristics and architectural parameters The hybrid scheme is shown to be effective in improving the performance of forwarding in reduced cache sizes A compiler algorithm for data forwarding is presented that implements point-to-point forwarding, hybrid prefetching and forwarding, and selective forwarding Software and hardware support for prefetching and forwarding are also discussed

Memory latency reduction via data prefetching and data forwarding in shared memory multiprocessors

http://ieeexplore.ieee.org/iel5/4134098/4134171/04134188.pdf

A Testbed for Studying Parallel Programs and Parallel Execution Architectures

Citations

Execution-driven tools for parallel simulation of parallel architectures and applications

Visual parallel programming and determinacy: a language specification, an analysis technique, and a programming tool

Third annual collaborative editing workshop

Memory latency reduction via data prefetching and data forwarding in shared memory multiprocessors

1993 International Conference on Parallel Processing

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