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Patent

Accuracy monitor method of sampling cycle

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TLDR
In this paper, the presence or absence of a fault with high accuracy by measuring the width of a sampling cycle by the time decided by the executing time and frequency of an instruction word of a program and comparing the measured value with a standard for decision.
Abstract
PURPOSE:To monitor the presence or absence of a fault with high accuracy by measuring the width of a sampling cycle by the time decided by the executing time and frequency of an instruction word of a program and comparing the measured value with a standard for decision. CONSTITUTION:A circuit device which fetches the input information by sampling consists of a crystal oscillation circuit 1 which produces the master clock signal, a dividing circuit 2 which divides the master clock signal to produce the sample signal, a sample holding circuit 3 which fetches the analog input information synchronously with the sample signal, an A/D converting circuit 4, a memory 5 and a primary arithmetic unit 6. Then a specific program for monitor of sampling cycle accuracy is stored to a memory of the unit 6. This action is repeated by making use of the processing idle time. The specific program includes an increment instruction, a cycle shift deciding instruction and a branching instruction with repeats both said increment and deciding instructions. Then the program is measured by the time decided by the executing time of an instruction word. This measured value is compared with the upper and lower limit levels of the deciding standard. Thus the presence or absence of a fault can be monitored with high accuracy.

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