Patent
Analysis and optimization of array variables in compiler for instruction level parallel processor
TLDR
In this article, an expanded virtual register (EVR) data structure is provided comprising an infinite, linearly ordered set of virtual register elements with a remap() function defined upon the EVR.Abstract:
A process for optimizing compiler intermediate representation (IR) code, and data structures for implementing the process; the process is preferably embodied in a compiler computer program operating on an electronic computer or data processor with access to a memory storage means such as a random access memory and access to a program mass storage means such as an electronic magnetic disk storage device. The compiler program reads an input source program stored in the program mass storage means and creates a dynamic single assignment intermediate representation of the source program in the memory using pseudo-machine instructions. To create the dynamic single assignment intermediate representation, during compilation, the compiler creates a plurality of virtual registers in the memory for storage of variables defined in the source program. Means are provided to ensure that the same virtual register is never assigned to more than once on any dynamic execution path. An expanded virtual register (EVR) data structure is provided comprising an infinite, linearly ordered set of virtual register elements with a remap() function defined upon the EVR. Calling the remap() function with an EVR parameter causes an EVR element which was accessible as [n] prior to the remap operation to be accessible as [n+1] after the remap operation. A subscripted reference map comprising a dynamic plurality of map tuples is used. Each map tuple associates the real memory location accessible under a textual name with an EVR element. A compiler can use the map tuple to substitute EVR elements for textual names, eliminating unnecessary load operations from the output intermediate representation.read more
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Patent
Process for converting programs in high-level programming languages to a unified executable for hybrid computing platforms
TL;DR: In this paper, the authors present a system and method for compiling computer code written to conform to a high-level language standard to generate a unified executable containing the hardware logic for a reconfigurable processor, the instructions for a traditional processor (instruction processor), and the associated support code for managing execution on a hybrid hardware platform.
Patent
Method and apparatus for analyzing computer code using weakest precondition
TL;DR: In this paper, an analyzer for maintaining and analyzing source code is described, which includes a software translator for converting conventional source code into an intermediate language, slicing capability based upon weakest precondition determination, dual direction flow analysis and incorporation of a computational model to facilitate iterative code.
Proceedings ArticleDOI
Generating local addresses and communication sets for data-parallel programs
TL;DR: This work shows that for an array affinely aligned to a template, the local memory access sequence for any processor is characterized by a finite state machine of at most at most k states, and extends the framework to handle multidimensional arrays.
Patent
Method and apparatus for an improved optimizing compiler
TL;DR: In this paper, an optimizing compiler process and apparatus for more accurately and efficiently identifying live variable sets in a portion of a target computer program, so as to more efficiently allocate registers in a computer central processing unit.
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Method of generating application specific integrated circuits using a programmable hardware architecture
TL;DR: In this article, a high-level language compiler is provided that compiles a user created high level language program that defines the application specific integrated circuit and parses the program into a plurality of microtasks for instructing the plurality of task engines to implement the application-specific integrated circuit.
References
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TL;DR: In this article, an expert system shell is proposed to compute functions of variables in response to numeric or symbolic data values input by a user, allowing many different types of variables, including numeric and symbolic types.
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Parallelization compile method and system
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Compiling method for determining programs to be executed parallelly by respective processors in a parallel computer which transfer data with a data identifier to other processors
TL;DR: In this paper, a compiler for generating from a serially processed type source program described in a high level language the object codes to be executed in parallel by a parallel processor system which is composed of a plurality of processors marked with respective identification numbers is adopted.
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Compiling method for vectorizing multiple do-loops in source program
Kyoko Iwasawa,Yoshikazu Tanaka +1 more
TL;DR: In this paper, a compiling method is provided for vectorizing outer sides of multiple loops which are not tight, and the compiler inserts control statements to assure initial values and end values for the loops are preserved minimizing the size of the working arrays, and vectorizing multiple loops for each loop level.
Patent
Data processing device
TL;DR: In this paper, a data processing device equipped with a plurality of arithmetic units is described, which can be used to process a number of instructions in parallel by the same arithmetic units.