Clock break detection circuit

TLDR: In this article, a low-speed clock break detection circuit with only digital elements is presented, where high-speed reference clocks and low-time frame clocks are sent from a master clock unit.

Abstract: PURPOSE:To reduce a cost and a space by constituting a low-speed clock break detection circuit with only digital elements by utlizing points where high-speed reference clocks and low-speed frame clocks are sent from a master clock unit. CONSTITUTION:The existence of coming of frame clocks are stored in shift registers 72 and 73 by anti-phase clocks of the reference input, which pass through gate 71, while shifting them successively. The output is inputted to exclusive OR gate 74, so that the output of reference input 2-clock components gate 74 becomes high- level after the frame clock comes. At this time, counter 78 is reset and does not reach 1023; however, when even one of frame clocks lacks, counter 75 reaches 1023, and a pulse appears at the 1023 output of decoder 76 to set a flip flop through OR gate 79, and alarm is indicated to software similarly to reference clock break.