scispace - formally typeset
Patent

Digitally adjustable quantization circuit

Reads0
Chats0
TLDR
In this paper, a quantization circuit comprises an input node and a comparator array, where each comparator of the array is coupled to the input node, and a control node is coupled with the voltage divider arrangement to adjust the threshold voltage for at least one comparator in response to a control signal at the control node.
Abstract
Apparatus and methods are provided for converting an analog input signal to a digital output value. A quantization circuit comprises an input node and a comparator array, wherein each comparator of the comparator array is coupled to the input node. A voltage divider arrangement is coupled to the comparator array and configured to establish a respective threshold voltage for each comparator of the comparator array. The comparator array generates a digital code based on the input signal and the respective threshold voltage for each comparator. A control node is coupled to the voltage divider arrangement, wherein the control node and the voltage divider arrangement are cooperatively configured to adjust the threshold voltage for at least one comparator of the comparator array in response to a control signal at the control node.

read more

Citations
More filters
Patent

System and methods for data compression and nonuniform quantizers

TL;DR: In this paper, an optical network includes a transmitting portion configured to encode an input digitized sequence of data samples into a quantized sequence having a first number of digits per sample, and a receiving part configured to receive and demodulate the modulated sequence from the digital optical link.
Patent

Receiver with adjustable reference voltages

TL;DR: In this article, an analog-to-digital converter with adjustable reference voltages that are calibrated to account for process variations is described. But the reference generator adjusts voltage levels of the set of N reference voltage levels based on one or more control signals.
Patent

Timing recovery for digital receiver with interleaved analog-to-digital converters

Yu Kou
TL;DR: In this paper, a first analog to digital converter converts an analog signal into first digital samples under control of a first sampling clock and a second clock generator adjusts the phase of the second sampling clock based on at least one second phase control signal.
Patent

Short detection circuit and display device including the same

TL;DR: In this paper, a short detection circuit includes a reference voltage generator, a comparison voltage generator and a short detector that determines whether a target line transferring the short detection target voltage is electrically shorted based on the comparison result voltage.
Patent

Method and apparatus for excess loop delay compensation in delta-sigma modulator

TL;DR: A delta-sigma modulator includes a signal subtraction circuit, a loop filter, a quantizer, a digital-to-analog converter (DAC), and a control circuit as mentioned in this paper.
References
More filters
Patent

Analog-to-digital converter

TL;DR: In this article, the authors propose to ensure excellent differential linearity even in case the clock frequency is increased to increase the converting speed, by delaying the start time point for discharge of a constant current within a prescribed range of the clock number and subtracting the number of delayed clocks from the count value of a counter.
Patent

Multilevel analog to digital data converter having dynamic element matching in a reference data path

TL;DR: In this article, a delta sigma analog-to-digital converter with dynamic element matching circuitry is described, where reference voltages are switched to specific comparators according to control signals from switch control circuitry.
Patent

Gain control in a signal path with sigma-delta analog-to-digital conversion

TL;DR: Automatic gain control is provided in a sigma-delta analog-to-digital converter as mentioned in this paper, where an amplifier and an attenuator are provided by an amplifier within the continuous loop prior to quantization.
Patent

Delta sigma modulator analog-to-digital converters with quantizer output prediction and comparator reduction

TL;DR: The quantizers of delta sigma modulators in the signal processing systems described in this paper use a reduced set of comparators for quantization by predetermining and maintaining a maximum per cycle deviation d between a loop filter output signal V LF (t) and a predicted quantizer output signal q est.
Patent

Delta sigma modulators with comparator offset noise conversion

TL;DR: In this article, a comparator offset converter is proposed to improve the signal-to-noise ratio of delta sigma modulators by maintaining a 1 : 1 ratio of reference signal to comparator input terminals and randomizing the reference signalto-comparator input terminal associations.
Related Papers (5)