Flip-flop circuit

TLDR: In this paper, the authors proposed to increase the maximum operating frequency by connecting a resistor and a peaking circuit in series as a load of a differential pair transistor (TR) so as to cancel the effect of the stray capacitance in existence to the collector of the differential TR.

Abstract: PURPOSE:To increase the maximum operating frequency by connecting a resistor and a peaking circuit in series as a load of a differential pair transistor (TR) so as to cancel the effect of the stray capacitance in existence to the collector of the differential TR. CONSTITUTION:The impedance viewing toward the emitter of a TR Q9 at a prescribed high frequency region is inductive in a circuit comprising the load TR Q9 and resistors RC1, RB1 in an emitter coupling logic FF circuit subject to circuit integration to form a peaking circuit 10 having a characteristic known as the peaking characteristic. Similarly, a load TR Q10, resistors RC2, RB2 form a peaking circuit 11 similarly. Thus, the effect by the stray capacitance existing between collector connecting points N1, N2 and the ground is cancelled. Thus, the frequency characteristic of the FF circuit is improved and the self-running frequency being an indication of the maximum operating frequency is improved remarkably. Even with a clock input exceeding 1MHz, the circuit is operated stably.