scispace - formally typeset
Patent

Flip-flop circuit with low-leakage transistors

Reads0
Chats0
TLDR
In this article, a flip-flop circuit with low-leakage transistors is proposed to pass a data signal for the logic circuit along a signal path, and a capacitor is coupled between the signal path and ground to store a value of the data signal.
Abstract
Embodiments include apparatuses, methods, and systems for a flip-flop circuit with low-leakage transistors. The flip-flop circuit may be coupled to a logic circuit of an integrated circuit to store data for the logic circuit when the logic circuit is in a sleep state. The flip-flop circuit may pass a data signal for the logic circuit along a signal path. A capacitor may be coupled between the signal path and ground to store a value of the data signal when the logic circuit is in the sleep state. A low-leakage transistor, such as an IGZO transistor, may be coupled between the capacitor and the signal path and may selectively turn on when the logic circuit transitions from the active state to the sleep state to store the value of the data signal in the capacitor. Other embodiments may be described and claimed.

read more

Citations
More filters
Patent

SMF and AMF relocation during UE registration

TL;DR: In this article, a target AMF receives a first message requesting a handover of a wireless device from a source AMF, and a second message requesting creation of first PDU session(s) between the UPF and the wireless device.
Patent

Monitoring and reporting service performance in roaming scenario

TL;DR: In this article, a HPCF receives from an application function, a first message requesting to subscribe to a QoS event for a data flow of a wireless device, and sends to a VPCF, a second message comprising the QoS reporting policy.
Patent

State retention circuit that retains data storage element state during power reduction mode

TL;DR: In this paper, a semiconductor device that retains a state of a data storage element during a power reduction mode including supply rails and voltages, and a storage latch and a retention latch both powered by retention supply voltage that remains energized during power reduction is presented.
References
More filters
Patent

Nonvolatile latch circuit and logic circuit, and semiconductor device using the same

Kiyoshi Kato, +1 more
TL;DR: In this paper, a nonvolatile latch circuit and a semiconductor device using the latch circuit was proposed, which includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element; and a data holding portion for holding data of the latch portion.
Patent

Memory device and semiconductor device

TL;DR: In this paper, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory devices.
Patent

Power switch design and method for reducing leakage power in low-power integrated circuits

TL;DR: In this article, power switching circuits and power management techniques are provided that can reduce static power of ICs, including digital core processors, including a footer between the core and a ground rail and at least two additional power-gating transistors parallel to the footer.
Patent

Programmable logic device with programmable wakeup pins

TL;DR: In this paper, a programmable logic device (PLD) adapted to enter a low power or sleep mode with programmable wakeup pins in a wakeup group of pins is disclosed.
Patent

Memory element and signal processing circuit

TL;DR: In this article, a memory element including a pair of inverters, a capacitor which holds data, and a switching element which controls accumulating and releasing of electric charge of the capacitor are provided.