Patent
Heterogeneous multi-core digital signal processor for orthogonal frequency division multiplexing (OFDM) wireless communication system
Qin Wang,Li Xu,Shaobo Shi +2 more
TLDR
In this article, a heterogeneous multi-core digital signal processor for an OFDM wireless communication system is presented. But the design of a dedicated task scheduling unit or a master control processor is eliminated, and the expandability and simplicity of the multicell processor are ensured.Abstract:
The invention provides a heterogeneous multi-core digital signal processor for an orthogonal frequency division multiplexing (OFDM) wireless communication system, and relates to the field of microprocessor system structures. The processor consists of a set of processor cores which are distributed in a row, wherein the processor cores can be divided into different types according to computing capability; the different types of processor cores are mutually connected in an open loop interconnection mode; the processor cores are very long instruction word (VLIW) processors; data transmission among the processor cores is realized by a shared memory; and control signals are transmitted through bus control units in the processor cores and task scheduling buses outside the processor cores. Each processor core can receive task scheduling information from other processor cores, so that the design of a dedicated task scheduling unit or a master control processor is eliminated, and the expandability and simplicity of the multi-core processor are ensured; and the structure of the multi-core processor can effectively accord with the characteristic of wireless communication baseband processing and achieves high performance per watt.read more
Citations
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Phase-locked loop parameter adjustment method, Bluetooth module, Bluetooth slave device and Bluetooth system
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Patent
Method and device for carrying out wireless communication scheduling on heterogeneous multi-core system on chip
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Data processing method, processor, and data processing device
Nan Li,Linchun Wang,Hongfei Chen +2 more
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References
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Patent
Arrangements facilitating ordered transactions
TL;DR: Arrangements facilitating ordered transactions, e.g., ordered writes, in a packet switch system having multiple switch elements have been discussed in this paper, where the authors consider the case of multiple switches.
Patent
Single chip multi-processor shared data storage space access method
TL;DR: In this article, a visit method for sharing data storing space of a single chip multi-processor, which uses the data space sharing of high 128 bytes in each sub-processor for transmission of command and data among the processors, and a sharing data memory interruption (SDMI) is added in the sub-processors, and the SDMI and an arbiter are effectively combined as a visit mechanism of a data sharing memory for solving competition which exists in data exchange among each subprocessor.
Patent
Embedded symmetric multiprocessor system
TL;DR: The embedded symmetric multiprocessor (ESMP) as discussed by the authors is a hardware architecture that allows the program stream at the application task or process level to be divided among different central processing units without change to the application code.
Patent
Multicore architecture supporting dynamic binary translation
Zhiying Wang,Lai Xin,Li Shen,Fan Xu,Wei Chen,Chen Xuhao,Zhong Zheng,Zhu Tianlong,Lu Huajun,You Liangshuai +9 more
Patent
Multi-core processor
TL;DR: In this paper, a multi-core processor consisting of a plurality of processor sets and a debugging configuration unit is presented, where the processor sets are in row distribution, each processor set comprises a main processor and a pluralityof slave processors, and all the main processors and the slave processors are ultra-long instruction word processors.