Patent
Latch circuit provided with clock signal level conversion function, and flip-flop circuit
Hamada Mototsugu,Kuroda Tadahiro +1 more
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TLDR
In this article, a flip-flop circuit provided with a master latch circuit ML and a slave latch circuit SL is driven by voltage VDD1 and ground voltage, and a clock signal level conversion circuit CLC is arranged on a front stage for inputting the clock signal to the FF circuit.Abstract:
PROBLEM TO BE SOLVED: To prevent leakage current from flowing through a flip-flop circuit. SOLUTION: This flip-flop circuit provided with a master latch circuit ML and a slave latch circuit SL is driven by voltage VDD1. A clock signal CK is amplituded between voltage VDD2 lower than the voltage VDD1 and ground voltage. A clock signal level conversion circuit CLC is arranged on a front stage for inputting the clock signal to the FF circuit. The circuit CLC boosts the voltage VDD2 of the clock signal CK to the voltage VDD and then inputs a high voltage clock signal CK to the FF circuit. Consequently the leakage current can be prevented from flowing through the flip-flop circuit.read more
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