Patent
Method of fabrication of a low capacitance self-aligned semiconductor electrode structure
Reads0
Chats0
TLDR
In this paper, the first electrodes are protected by silicon nitride and a low resistivity silicon layer is grown over the semiconductor wafer, forming epitaxial regions over the second electrodes of a polycrystalline region over protected portions of the wafer.Abstract:
Semiconductor electrode structure with low parasitic capacitance and method for forming low capacitance first and second electrodes in a semiconductor device, such as a static induction transistor, while avoiding the requirement for precision mask alignment and mask to mask registration. During formation of electrode contacts, the first electrodes are protected by silicon nitride and a low resistivity silicon layer is grown over the semiconductor wafer, forming epitaxial regions over the second electrodes of a polycrystalline region over protected portions of the wafer. The silicon layer is selectively etched by a mixture which removes the polycrystalline region but does not appreciably affect the epitaxial regions. Second electrode metallic contacts are made in enlarged regions of the second electrodes where mask alignment is not critical. The reduction in contact window overlap by metallic contacts reduces parasitic capacitance.read more
Citations
More filters
Patent
Method of making vertical channel field controlled device employing a recessed gate structure
Bantval Jayant Baliga,R.P. Love +1 more
TL;DR: In this article, a vertical channel junction gate electric field controlled device (e.g., a field effect transistor or a field controlled thyristor) is constructed with a semiconductor base region layer and a plurality of grooves having vertical walls formed in the upper surface of the base region.
Patent
Symmetric self-aligned processing
Paul M. Enquist,D.B. Slater +1 more
TL;DR: In this paper, a method of manufacturing a semiconductor device using simplified processing and eliminating and/or minimizing the extrinsic parasitic elements of the device is presented. But, the method is particularly suited for manufacturing heterojunction bipolar transistors where the extrinic parasitic base resistance and the intrinsic base-collector and base-emitter capacitances can be virtually eliminated and the base contact resistance can be greatly reduced.
Patent
Method of fabricating junction field effect transistors
Adrian I. Cogan,Izak Bencuya +1 more
TL;DR: In this paper, the junction field effect transistor (JFET) was used to produce narrow channel regions at a depth beyond the surface layer while limiting the lateral extensions of the P-type gate regions adjacent to the surface.
Patent
Method of manufacturing heterojunction transistors with self-aligned metal contacts
Paul M. Enquist,D.B. Slater +1 more
TL;DR: In this paper, a self-aligned contacts are formed to the base and emitter regions using the lateral overhang portions which provide separation between the emitter structure and the contacts to the Base layer.
Patent
Method of making junction field effect transistor of static induction type
Izak Bencuya,Adrian I. Cogan +1 more
TL;DR: In this paper, an epitaxial layer of high resistivity N-type silicon is grown on a substrate of low resistivity silicon and the remaining silicon nitride is removed, and metal contacts are applied to the gate ridges, the source ridges and the substrate.
References
More filters
Patent
Field effect transistor having a linear attenuation characteristic and an improved distortion factor with multiple gate drain contacts
TL;DR: In this paper, a field effect transistor with two electrodes and distributed resistance there between is described as an attenuator when a main signal is applied across one drain electrode and a source and a control voltage is applied between a gate and the source.
Patent
Method of manufacturing integrated injection logic semiconductor devices utilizing self-aligned double-diffusion techniques
TL;DR: In this paper, a P type semiconductor layer is formed on an N type semiconducting layer by vapour epitaxial growth technique, an insulating film is formed, and a grid shape first opening is provided through the film.
Patent
Process for forming sloped topography contact areas between polycrystalline silicon and single-crystal silicon
TL;DR: In this paper, a sloped tip of a single crystal silicon material located at the end of a polycrystalline silicon layer and making contact with the single-crystal silicon substrate is described.
Patent
Method for manufacturing junction type field-effect transistors
Kiyoshi Aoki,Hisao Kamo +1 more
TL;DR: In this article, a gate region is formed by diffusing impurities through openings of different masks, where one portion over which a source electrode extends and the other part over which allows an essential gate function.
Patent
Process for fabricating a vertical static induction device
TL;DR: In this paper, a method of fabricating a vertical static induction semiconductor device comprising depositing a polycrystalline silicon film on a single crystal silicon layer, and forming an insulating film comprised of silicon nitride on the poly crystal silicon film is presented.