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Multi-processor system for selecting a processor which has successfully written it's ID into write-once register after system reset as the boot-strap processor

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TLDR
Bootstrap processor selection as discussed by the authors employs system logic having a memory-mapped sticky register, e.g. write-once, register, multiple processors, and a firmware routine through which the processors may store values to and load values from the sticky register.
Abstract
A bootstrap processor selection mechanism for a computer system employs system logic having a memory-mapped sticky, e.g. write-once, register, multiple processors, and a firmware routine through which the processors may store values to and load values from the sticky register. When a reset event is detected, the processors vie for access to the sticky register, using the firmware routine. The first processor that successfully stores its associated processor ID to the sticky register, locks the register against subsequent store operations by the remaining processors. Each processor loads the value stored in the sticky register and compares it with its processor ID to determine whether it is the bootstrap processor.

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References
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Patent

Fault-tolerant boot strap mechanism for a multiprocessor system

TL;DR: In this article, the authors propose a boot protocol in which each processor compares a vector field of a boot message issued on the serial bus by a first processor with an ID of the processor; a match indicating that the first processor is a bootstrap processor (BSP).
Patent

Multi-processor resource locking mechanism with a lock register corresponding to each resource stored in common memory

Bruce D. Buch
TL;DR: In this paper, the authors propose a method and apparatus to reduce bus usage and to increase resource locking protocol compatibility within a heterogeneous processing environment, where lock indicators are maintained in stores designated as lock registers and access to a resource is gained by any processor depending upon the status of a lock register associated with that resource.
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Bootstrap processor selection architecture in SMP system

TL;DR: In this paper, a method for selecting a bootstrap processor from among the processors of a multiprocessor system is presented, where each processor has an identity code and each processor that is eligible to serve as the boot-strap processor sends an election message to processors having lower valued identity codes.
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Memory testing in a multiple processor computer system

TL;DR: In this paper, a shared memory (RAM) test is performed by partitioning the memory (10) and allocating the memory portions to respective processors (20a-20d) in the system.