scispace - formally typeset
Patent

Parallel process system

TLDR
In this article, the information transfer path lij is provided between every two processors which differ only by one bit when the numbers are given to plural units of processors and then the number is displayed in the binary number.
Abstract
PURPOSE:To secure a parallel operation such as the butterfly operation or the like by providing the information transfer path between every two processors which differ only by one bit when the numbers are given to plural units of processors and then the numbers are displayed in the binary number CONSTITUTION:Numbers 0 - 7 are given to processors 10 - 17, and these numbers are displayed in the binary number In this case, information transfer path lij is provided between every two processors which differ only by one bit For example, l01 displays the information transfer path between processor 0 and 1 In the same way, the information paths l02, l04, l13, l15; l23, l26; l37; l45, l45, l47; l57; l67 are provided In case the distance between processors (0 and 7) in which the 3 bits are all different, the operation is possible with 3 steps at most And the memory is installed to each information transfer path to be passed through

read more

Citations
More filters
Patent

Communication network system

TL;DR: In this article, the transmission controllers in a high local area network (LAN) have a communication management function such that they send the data without grasping the situation on the transmission routes, independently check the trouble between the adjacent transmission controllers and specify the position of trouble.
Patent

Communication system in parallel computer

Morio Ikesaka, +1 more
TL;DR: In this article, the authors considered the case that a data is desired to be transmitted from a PE0 to other PEs, and the relative position of other PE's is obtained around the PE0 and used as relative position information.
Patent

Parallel processing computer

Nogi Tatsuo
TL;DR: In this article, the authors propose a parallel computer in the hierarchy constitution consisting of one main processor, a plurality of N sets of subprocessors and n sets of slave processors, where a subprocessor SU-k is in bus connection with the subsystem consisting of AU-j, AU-k, and a buffer memory plate (i,j)k.
Patent

One-to-multiple type message transmission system

TL;DR: In this article, the authors propose to suppress an influence when a node defect occurs by transmitting a message to a plurality of receiving nodes without causing response explosion and grasping message receiving situations of the receiving nodes in one-to-multiple type message transmission.
Patent

Processor connecting device

Maeda Akira
TL;DR: In this article, the authors propose a scheme to enable all processors to transfer data at a time with no mutual conflict by providing a connecting means corresponding to each processor in a rectangular form of (4X4).