Proceedings ArticleDOI
PCB layer reduction to save system BOM cost in an Intel Haswell-EP server platform
Ruonan Wang,Hao Wang,Yuan-Liang Li,Jiangqi He,Wei Xu,Xiaoning Ye,Zhenhua Yuan +6 more
- pp 187-190
TLDR
Through a practical design on an Intel Haswell-EP server platform in Huawei, a 4-PCB-layer reduction is achieved compared to the original board, saving system bill-of-material cost effectively.Abstract:
Many Intel PRC customers worked on low-cost solutions in server platforms. This paper introduced a method to investigate dual strip line performance on high-speed interfaces like DDR and PCIe. Through a practical design on an Intel Haswell-EP server platform in Huawei, we achieved 4-PCB-layer reduction compared to the original board, saving system bill-of-material cost effectively. Pre- and post-layout simulations were performed to evaluate design risks on signal integrity and power integrity. The electrical validations on board proved the comparable system performance of the low-cost design with the original board and Intel customer reference board, correlating to simulation results as well.read more
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Proceedings ArticleDOI
Power Delivery Resonant Virus: Concept and Applications
TL;DR: A very interesting yet powerful virus that can cause chip failure instead of directly injecting hardware sub-circuits that require layout modification or split manufacturing, which uses resonant noise in power delivery system as the weapon.