Patent
Pll frequency synthesizer and method for controlling the pll frequency synthesizer
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TLDR
In this paper, a PLL frequency synthesizer is provided with a voltage detector which detects the present value of a control voltage applied to a voltage-controlled oscillator, a storage device which stores in advance the set values of a plurality of control voltages corresponding to the set value of the plurality of frequency dividing numbers set in a frequency divider, and a voltage value comparator (8) which compares the present values of the detected control voltage detected by the detector (9) with the setvalue of the control voltage outputted from the device (7), and a switchingAbstract:
A PLL frequency synthesizer which is provided with a voltage detector (9) which detects the present value of a control voltage applied to a voltage-controlled oscillator (6), a storage device (7) which stores in advance the set values of a plurality of control voltages corresponding to the set values of a plurality of frequency dividing numbers set in a frequency divider (2) and outputs the set value of the control voltage corresponding to the frequency dividing number set in the frequency divider by selecting the set value out of the set values of the control voltages, a voltage value comparator (8) which compares the present value of the control voltage detected by the detector (9) with the set value of the control voltage outputted from the device (7), and a switching circuit (10) which outputs either the phase difference signal generated by means of a phase comparator (3) and representing the phase difference between the phase of a frequency dividing signal outputted from the divider (2) and that of a reference frequency signal or the output signal of the comparator (8) by switching. The comparator (8) controls the circuit (10) so that a charge pump (4) can be driven with its own output signal when the difference between the present value of the detected control voltage and the set value of the control voltage from the device (7) is larger than a prescribed value or with the phase different signal from the phase comparator (3) when the difference is not larger than the prescribed value.read more
Citations
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Pll loop bandwidth calibration
Troy Stockstad,Tracy Hall +1 more
TL;DR: In this paper, the authors describe a system and methodologies that facilitate calibration of the loop bandwidth of a phase-locked loop (PLL) by adjusting only parameters of a charge pump of the PLL without requiring individual control mechanisms for each element.
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References
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Patent
Fast settling phase locked loop
TL;DR: In this paper, an analog error correction signal is generated by sampling any residual error coming from the phase detector, and generating the analog correction signal to counter the residual error, and the switch between a phase detector output and a VCO input to open the PLL during a frequency change is provided.
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Phase lock loop prepositioning apparatus with feedback control
TL;DR: In this paper, a feedback-controlled current pump is coupled to the loop filter capacitor of a phase lock loop to provide a coarse prepositioning voltage and thereby accelerate the lockup process on a new frequency.
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Pll anomaly detector circuit
Yasumori Hibi,Katsuji Kobayashi +1 more
TL;DR: In this paper, the output of phase comparator 4 is applied to VCO 6 through LPF 5, and output VCNT of LPF5 is compared with lower limit Vref1 of the use voltage of the VCO by comparator 11 and is compared to upper limit VRef2 in comparator 12.
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TL;DR: In this article, the authors proposed a high speed synchronization frequency synthesizer in which synchronization is taken at high speed even under a temperature change, thereby obtaining a high frequency signal with a desired frequency quickly.
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TL;DR: In this paper, a phase synchronizing loop circuit whereby lock-up time at the time of channel changeover is shortened in a phase synchronized loop circuit used for a radio equipment utilizing multiple channel frequencies is presented.