Pulse delay circuit

TLDR: In this article, a master clock signal CKM is input to a signal control part 1 for the number of delay stages of the pulse delay circuit and a data signal XD of a necessary delay time value represented as the rate to the master clock rate is also inputted.

Abstract: PURPOSE:To perform pulse delay control over a delay time shorter than the master clock rate of a system and to output a stable delay pulse signal from the digital system by correcting variations in source voltage and temperature and variance in manufacture process on circuit system basis. CONSTITUTION:A master clock signal CKM is inputted to a signal control part 1 for the number of delay stages of the pulse delay circuit and a data signal XD of a necessary delay time value represented as the rate to the master clock rate is also inputted. This control part 1 outputs the corrected delay-stage number numeral yact of a unit delay circuit. This delay-stage number numeral yact is applied to a delay pulse signal selection part 2 and a selection reference pulse PB is inputted to the input terminal of the 1st stage of a unit delay circuit. Then, output pulses of (n) stages of unit delay circuits 31-3n connected in series are selected with switched 41-4n for unit delay circuit output pulse selection which are controlled by a decoder 5 for output pulse selection, thereby outputting the stable delay pulse PD.