Patent
Signal generating circuit
TLDR
A signal generating circuit includes a switching circuit that includes two series-connected circuits each of the latter includes an enhancement-type MOS FET and a depletion-type FET connected between one terminal of a power source and a junction point of the series connected circuits The junction point is used as the output terminal of the switching circuit as mentioned in this paper.Abstract:
A signal generating circuit includes a switching circuit that includes two series-connected circuits Each of the latter includes an enhancement-type MOS FET and a depletion-type MOS FET connected between one terminal of a power source and a junction point of the series-connected circuits The junction point is used as the output terminal of the switching circuitread more
Citations
More filters
Patent
Mosfet logical circuit with increased noise margin
TL;DR: In this article, the first and second circuits of a logic circuit are shown to have a threshold voltage larger than the threshold voltage of the first circuit and a gate connected to the output terminal.
Patent
CMOS buffer circuit
TL;DR: In this article, a CMOS logic input circuit comprises two complementary transistor pairs, TR1 and TR2; TR3 and TR4 coupled in series between the supply rails, such that the switching threshold is substantially independent of transistor characteristics.
Patent
Generator of reset pulses upon the rise of the power supply for CMOS-type integrated circuits
TL;DR: In this paper, the generator has an input stage (I) including a voltage divider for dividing the voltage between the power supply and the ground, having a node constituting the output of the input stage, and by a positive-feedback threshold loop, driven by another node of the voltage dividers to make the voltage in the output node rise sharply when the voltage level in the other node exceeds a threshold, and a former of output pulses (F) comprising a second Schmitt trigger (T2) is driven by circuit means adapted to directly apply to the second Sch
Patent
MOS IC Oscillation circuit
Daijiro Kubo,Masaru Hashimoto +1 more
TL;DR: A MOS IC oscillation circuit comprising a circuit including a MOS FET and a resistor connected in series between a power source and ground, a capacitor one end of which was connected to the junction between both said components and the other end is connected to said power source or the ground, and a Schmitt trigger circuit receiving an input signal from the junction and produces an output signal which controls "on-off" operation of the FET.
Patent
Mos-input buffer with hysteresis
TL;DR: An MOS input buffer circuit includes an input connected to the gate electrode of an enhancement mode input MOSFET, and the drain of the MOS FET is connected to output of the input buffer as discussed by the authors.
References
More filters
Patent
CMOS voltage controlled oscillator
TL;DR: In this paper, a CMOS voltage controlled oscillator is described, which is a linear CMOS circuit and exhibits an infinite current gain, a near infinite input impedance, a very high voltage gain with a corresponding low power consumption.