Patent
Testing of a semi-conductor integrated circuit device
Reads0
Chats0
TLDR
In this paper, a semi-conductor integrated circuit device is implemented in the test mode of the internal circuit due to the fact that it permits a part of region belonging to the integrated circuit devices to allocate to outer memory space.Abstract:
In a semi-conductor integrated circuit device, a memory space provided with the integrated circuit device is not occupied by space for testing the integrated circuit device as the testing memory space. In the test mode of the semi-conductor integrated circuit device, test of internal circuit is capable of being implemented due to the fact that it permits a part of region belonging to the integrated circuit device to allocate to outer memory space. While in a normal operation mode, degree of freedom of design of the integrated circuit device is increased by releasing the testing memory space.read more
References
More filters
Patent
Single chip MOS computer with expandable memory
TL;DR: In this article, an MOS digital computer incorporated on a single chip (monolithic structure) which includes a central processing unit (CPU), random access memory (RAM), and a programmable read-only memory (PROM).
Patent
Microprocessor with self-diagnostic test function
TL;DR: In this article, a self-diagnostic test function is provided in a microprocessor, which includes an input circuit for inputting at least a macro instruction and information necessary for selfdiagnostic testing stored in an external memory; a decoder for decoding the inputted macro instruction; a micro instruction ROM for storing micro instructions; an incrementer for generating an incremented address by incrementing the address of the received address of an instruction ROM by 1.
Patent
IC card having fault checking function
TL;DR: In this article, the authors present an IC card having a fault check function comprising a ROM having test areas of the number corresponding to memory address lines so that predetermined various data necessary for executing a fault checking are recorded in advance into the test areas, means for successively reading out the data previously recorded in the test area, detecting coincidence of the respective data successively read out by the reading-out means with corresponding ones of said predetermined data, and means for making judgement as to whether a fault exists or not on the basis of a result of detection by the coincidence detecting means.