Patent
Triplicated clock distribution device for use when each clock signal comprises a synchonization signal
Reads0
Chats0
TLDR
In this paper, a triplicated clock distribution device, where each clock signal comprises a synchronization signal, comprises three slave clocks connected to receivers, each slave clock comprises a clock generator and a synchronization generator and delivers a clock signal incorporating a synchronous signal the frequency of which is half that of the clock signal.Abstract:
A triplicated clock distribution device, for use where each clock signal comprises a synchronization signal, comprises three slave clocks connected to receivers. Each slave clock comprises a clock generator and a synchronization generator and delivers a clock signal incorporating a synchronization signal the frequency of which is half that of the clock signal. Each receiver comprises a clock regenerator and a synchronization regenerator which respectively deliver a clock signal and a synchronization signal to user circuits to which the receiver is connected.read more
Citations
More filters
Patent
Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices
Takashi Hotta,Kozaburo Kurita,Masahiro Iwamura,Hideo Maejima,Shigeya Tanaka,Tadaaki Bandoh,Yasuhiro Nakatsuka,Kazuo Kato,Sin-ichi Sinoda +8 more
TL;DR: An information processing system having an original clock oscillator for delivering at least one original clock signal defined as a first clock signal and a plurality of information processing units supplied with the original clock signals is defined in this article.
Patent
Digital clock buffer circuit providing controllable delay
TL;DR: In this paper, a clock buffer circuit that generates a local clock signal in response to a system clock signal was proposed, where the buffer control circuit provides a variable delay so that the local clock signals have a selected phase relationship in relation to the system clock signals.
Patent
Process control interface system having triply redundant remote field units
Fernandez G Paul,Dean W Gaudreau,Gregory J Gavit,Robert S Glaser,Tim Grai,Donald Grinwis,Robert S. Hoy,Robert J. Hozeska,Joseph Sheehan,Lowell S. Thomas +9 more
TL;DR: In this paper, a triply redundant input/output field computer unit is used to arbitrate both input and output signals in a process control interface system with a plurality of self-contained remotely located redundant field computer units connected to decision-making redundant process control computers.
Patent
Method and apparatus for stabilized data transmission
TL;DR: In this paper, the clock skew between the two subsystems is larger than one clock cycle by the method of the invention, and data can be accurately transmitted between two sub-systems even if clock skew can be more than one cycle.
Patent
Methods and circuits for synchronizing signals in a modular redundant fault tolerant computer system
TL;DR: In this article, a modular redundant fault-tolerant computer system is presented, in which clock signals for respective slices have a bounded skew with respect to one another, and each initial synchronization signal is used with an inverted version of each slice clock signals to produce, in each slice of a second layer of the circuit, a set of local synchronization signals for each slice.
References
More filters
Patent
Device for increasing the operational security of a duplicated clock
TL;DR: In this paper, the authors propose a scheme for increasing the operational security of a duplicated clock which comprises first and second clocks, where in each clock a selector circuit with inputs connected to a filter and signal shaping circuit of each clock.
Patent
Time base for synchronous generation of frame and clock pulses
Ollivier Yves,Jacob Michel +1 more
TL;DR: In this article, the authors proposed a high-security time base consisting of three synchronized generators which each deliver a clock signal 2h or a synchronizing signal Sy used for synchronizing frames.
Patent
Receiver for simultaneously transmitted clock and auxiliary signals
TL;DR: In this paper, a receiver for simultaneously transmitted clock signals of frequency F (HC) and auxiliary signals (HS), F =kf, k=2, 3, 4,..., said clock and SU signals being transmitted as a modified clock signal (HM) wherein one clock pulse is omitted every k clock pulses.
Patent
Signal distribution system for a time-division exchange
Philippe Duplessis,Michel Brusa +1 more
TL;DR: In this article, the authors present a distributed control architecture for a signal distribution signal for a time-division exchange, where terminal units (UT) and control units (UC) are connected via multiplex links (MX) and are synchronized by a time base (BDG) via clock signal distribution modules (MD).