Proceedings ArticleDOI
Verifying pipelined hardware using symbolic logic simulation
S. Bose,Allan L. Fisher +1 more
- pp 217-221
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TLDR
A method is presented for automated verification of synchronous pipelined circuits, based on symbolic simulation and the well-known program verification concept of representation functions, to allow straightforward formulation of readable and intuitive specifications.Abstract:
A method is presented for automated verification of synchronous pipelined circuits, based on symbolic simulation and the well-known program verification concept of representation functions. The use of representation functions to allow straightforward formulation of readable and intuitive specifications is demonstrated, along with the use of a symbolic switch-level simulator to automatically prove that a circuit meets its specification. As an example, a systolic stack with more than 5000 transistors can be formally verified in a few minutes on a VAX 8800. >read more
Citations
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Symbolic Boolean manipulation with ordered binary-decision diagrams
TL;DR: The OBDD data structure is described and a number of applications that have been solved by OBDd-based symbolic analysis are surveyed.
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Symbolic model checking for sequential circuit verification
TL;DR: In this paper, the temporal logic model checking algorithm of Clarke, Emerson, and Sistla is modified to represent state graphs using binary decision diagrams (BDD's) and partitioned transition relations.
Proceedings ArticleDOI
Sequential circuit verification using symbolic model checking
TL;DR: The model checking algorithm modified to represent a state graph using binary decision diagrams (BDD's) is able to handle a number of important liveness and fairness properties, which would otherwise not be expressible in CTL.
Journal ArticleDOI
Formal verification by symbolic evaluation of partially-ordered trajectories
TL;DR: The general theory underlying symbolic trajectory evaluation is presented and the application of the theory to the taks of verifying switch-level circuits as well as more abstract implementations are illustrated.
Book ChapterDOI
The Birth of Model Checking
TL;DR: "When the time is ripe for certain things, these things appear in different places in the manner of violets coming to light in early spring." (Wolfgang Bolyai to his son Johann in urging him to claim the invention of non- Euclidean geometry without delay
References
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Proceedings Article
Verifying a static RAM design by logic simulation
TL;DR: Three-valued modeling, where the third state X indicates a signal with unknown digital value, can greatly reduce the number of patterns that need to be simulated for complete veriication.