Showing papers on "40-bit encryption published in 1992"

Method and apparatus for encryption, decryption and authentication using dynamical systems

Abstract: A method and apparatus provide encryption, decryption and authentication of messages using dynamical systems. The method and apparatus preferably operate on an information stream which may comprise message information, authentication information, and random or pseudo-random information. The initial secret keys of the system are a collection of dynamical systems, at least one of which is irreversible. These keys operate on states of the dynamical systems into which the message has been encoded. To initialize the encryption, a subset of the secret keys are selected to be current keys, and the desired message is encoded into the initial states. Encryption continues over a plurality of cycles. During each cycle the current keys are applied either backward or forward in time to their current states, over a plurality of sub-cycles. If during an encryption cycle an irreversible dynamical system is iterated in the backward direction, the choice of antecedent states may either be made randomly or according to information from the input information stream. After all encryption cycles have been performed, the current states of the dynamical system constitute the ciphertext. The ciphertext may then be decrypted by a method similar to the encryption method. In the preferred embodiment, random noise is diffused into the plaintext during encryption, and eliminated during decryption. The apparatus of encryption and decryption in the preferred embodiment operates with parallel hardware using only bit operations and table lookup; it may thus be made to operate in an exceedingly fast manner.

An Ultra-high Speed Public Key Encryption Processor

Abstract: This paper describes the architecture and design of a public key encryption processor which implements the RSA algorithm with key lengths of512 bits. The chip, which is 6.2 by 4.2 millimetres, has been designed in a 0.7 micron CMOS, silicon on insulator process and has a target clock speed of 15OMHz. It is a self contained subsystem which interfaces directly to standard microprocessors and will be capable of encrypting at rates well in excess of 64k baud (for contractural reasons we are unable, at this time, to disclose the emct speed of operation).

Cryptographic apparatus and method for a data communication network

Abstract: A data transmission network (12) has a plurality of computers (14) interconnected by a transmission channel (12). The computer communicates with the channel through a security device (16) which encrypts and decrypts data. The device uses a key packet distributed over the network from which a new key is derived by using the encryption process within the device. The encryption process makes use of a data sequence or 'secret' peculiar to each domain so that the key generated in the domain is also peculiar to that domain. The key is changed as the encryption proceeds and upon completion of the data transmission. Each device periodically generates a new key for distribution over the network.

Yet another machine to break DES

Abstract: The Data Encryption Standard (DES) has been the subject of multiple attempts at breaking. As of this date no one has announced a method that will break DES with certainty. In this paper we do not consider a method but develop another machine. Many such machines have been proposed over the years (see [14]). Our machine makes use of current high-speed encryption chips in combination with hardware fuzzy comparers to automate the breaking process.