Showing papers on "Cache algorithms published in 1974"

Cache memory store in a processor of a data processing system

Abstract: A cache store located in the processor provides a fast access look-aside store to blocks of data information previously fetched from the main memory store. The request to the cache store is operated in parallel to the request for data information from the main memory store. A successful retrieval from the cache store aborts the retrieval from a main memory. Block loading of the cache store is performed autonomously from the processor operations. The cache store is cleared on cycles such as interrupts which require the processor to shift program execution. The store-aside configuration of the processor overlooks the backing store cycle on a store operand cycle and the cache store checking operations are performed next causing the cycles to be performed simultaneously.

An Investigation of Alternative Cache Organizations

Abstract: An investigation of the various cache schemes that are practical for a minicomputer has been found to provide considerable insight into cache organization. Simulations are used to obtain data on the performance and sensitivity of organizational parameters of various writeback and lookahead schemes. Hardware considerations in the construction of the actual cache-minicomputer are also noted and a simple cost/performance analysis is presented.

Apparatus for selectively clearing a cache store in a processor having segmentation and paging

Abstract: In a data processing system that uses segmentation and paging to access data information such as in a virtual memory machine, the cache store need not be entirely cleared each time an I/O operation is performed or each time the data in the cache has a possibility of being incorrect. With segmentation and paging, only a portion of the cache store need be cleared when a new page is obtained from the virtual memory. The entire cache store is cleared only when a new segment is indicated by the instruction. The cache store is selectively cleared of the information from the page whose data information is no longer needed by addressing each level of an associative tag directory to the cache store. The columns of each level are compared to the page address and if a comparison is signaled that column of the addressed level is cleared by clearing the flag indicating the full status of the column in the addressed level. Each level of the tag directory is addressed.

On the Modeling of Demand Paging Algorithms by Finite Automata

Abstract: Two finite automata are devised for modeling two classes of demand paging algorithms. The first one of one input and three outputs models the class of algorithms with a constant amount of allocated space. The second one of one input and six outputs models the class of algorithms with a variable amount of allocated space. Some evaluation techniques are developed following each model. The memory states of the first class algorithm with the Least Recently Used (LRU) replacement policy and the working set model of the second class are recursively defined by strings of the loaded pages. The adopted replacement policy and the state string updating procedure are imbedded in the recursive definition of memory states. Properties of some algorithms are developed to fit the finiteness assumption of a reference string.