Showing papers on "Carrier frequency offset published in 1989"

Far-echo cancellation in the presence of frequency offset (full duplex modem)

Abstract: A design is presented for a full-duplex echo-cancelling data modem based on a combined adaptive reference echo canceller and adaptive channel equalizer. The adaptive reference algorithm has the advantage that interference to the echo canceller caused by the far-end signal can be eliminated by subtracting an estimate of the far-end signal based on receiver decisions. This technique provides a novel approach for full-duplex far-echo cancellation in which the far echo can be cancelled in spite of carrier-frequency offset. To estimate the frequency offset, the system uses a separate receiver structure for the far echo which provides equalization of the far echo channel and tracks the frequency offset in the far echo. The feasibility of the echo-cancelling algorithms is demonstrated by computer simulation with realistic channel distortions and with 4800-b/s data transmission, at which rate the frequency offset in the far echo becomes important. >

Symbol carrier timing regeneration system

Abstract: PURPOSE:To widen a lead-in range for a carrier frequency offset and to simplify a circuit by providing a means which extracts a clock component by a decision directed system and a means which detects a carrier phase error. CONSTITUTION:The extracting means consisting of rectifying circuits 8 and 9 and a subtracting circuit 12 which rectify an in-phase and an orthogonal output and find their difference to obtain a frequency component a half as high as a symbol clock, and a decision directed type phase-locked loop (phase detectors 13 and 14, loop filter 19, VCO 20, orthogonal phase branching filter 15, LPF 17, comparator 18, and multiplier 16) generates the clock component through the nonlinear operation of an orthogonal demodulation output and extracts this component by the decision directed system. The detecting means consisting of a data detecting circuit 4, a multiplier 5, a sample holding circuit 6, and a switch 7 samples one of a couple of orthogonal demodulated data alternately at intervals of one clock at clock timing obtained by the loop, multiplies the value by the demodulated data, and detects the carrier phase error.