Showing papers on "Clock generator published in 1971"

Multiple phase clock generator circuit with control circuit

Abstract: A clock signal generating circuit including an oscillator circuit for supplying complementary square wave signals. A control circuit connected to the oscillator circuit for receiving the square wave signals and for, providing phase inversion and ordering of the signals in order to prevent phase overlap between the complementary signals. The output signals from the control circuit provide gating signals for a shift register. Output signals from the shift register are provided as input signals to output logic gates for generating multiple phase output signals. The output logic gates receive feedback signals from certain of the output logic gates for synchronizing the phase relationship between the multiple phase clock signals produced by the output logic gates.

Multiple phase clock generator circuit

Abstract: A clock signal generating circuit including an oscillator circuit for supplying complementary square wave gating signals to a multi-bit shift register. One shift register bit is required for each two clock pulse phases. Output signals from each bit position of the shift register are provided as input signals to NOR gates which also receive feedback input signals from the output terminals of certain of the NOR gates to synchronize the phase relationship between the multiple phase clock signals produced by the output logic gates. The output signals from the NOR gates comprise the multiple phase clock signals.

Improvements in or relating to systems for transmitting television signals

Abstract: 1,218,015. Television. NATIONAL RESEARCH DEVELOPMENT CORP. 12 March, 1968 [13 March, 1967], No. 11750/67. Heading H4F. [Also in Division G4] In a system for transmitting video signals, e.g. luminance information, by P.C.M., of the type in which a pseudo-random noise or "dither" signal is added to the video signal before quantization and is subtracted at the receiver after the video signal has been decoded (to minimize the effects of quantizing), the noise signal generator is synchronized with the sampled video input signal and includes a network supplied with pseudo-random binary noise signals which are each thereby weighted to provide a multilevel "dither" signal which by autocorrelation techniques is designed to give at the output of the system a power spectrum of increasing power density towards the high frequency end of the frequency band of the video signal. As shown in Fig. 1, a video signal from source 10 is applied, after suitable correction at 11, to an adder 12 where it is combined with a dither signal DS from generator 13, the combined output being supplied to a 2-bit 4-level quantizer P.C.M. encoder 14. The binary coded signal is transmitted via link 15 to a decoder 16 and the resulting analogue signal is supplied to an adder 17 which also receives the inverted dither signal from a generator 22 or alternatively over a separate channel 23, 24. The output of the adder consisting of the original video signal is supplied via conventional correction circuits 18 to a display device 19. The dither signal generator 13 includes a square wave generator 20 which is synchronized by the frame sync. pulses related to the source 10 and provides an output signal of amplitude equal to half a quantizing step at a frequency, for example, of 3MHZ. which is an odd multiple of half the line scan frequency of the video signal. The output signal level is arranged to average zero over two frames and is also arranged so that its phase is advanced and retarded alternately by 90 degrees at the start of each field so that interference is minimized. A shift register 21 controlled by a 6MHZ clock generator associated with the source 10 is provided with feedback, the output stages 10 and 11 in co-operation with resistance network 3R, 3R, 3R, R providing synchronized pseudorandom binary noise signals which are combined with the output of generator 20 to form the six level dither signal DS. In a modification of the pseudo-random noise generator 21, Fig. 2, the shift register is clocked at 1A5mHz. obtained from a 6mHz. clock signal via bi-stables 30, 31, and the outputs from stages 10 and 9 are modulated by the 3mHz. and 1A5mHz. square waves respectively from bi-stables 30, 31. The outputs of stages 9, 10, 11 are combined in a resistive network to provide a 6-level dither signal which is stated to have an improved noise spectrum. In a further arrangement, Fig. 3 (not shown), high-frequency pre-emphasis precedes the adder 12 and corresponding de-emphasis follows the adder 17 and a four-level dither signal is used. This is stated to provide a further reduction of quantizing noise.

Digital harmonic rejecting phase detector

Abstract: A digital harmonic rejecting phase detector inherently capable of rejecting substantially any even harmonic and with provisions for good rejection of at least one odd harmonic present in the input signal. The detector has a bidirectional counter system with a first half unidirectional counter and a second half unidirectional counter with transfer gating periodically transferring content of the first half counter to the second half counter. The bidirectional counter system accomplishes both an invert-noninvert function and the averaging function of a lowpass filter. The input signal is processed through a signal conditioner to a pulse density representation. A reference divider is provided developing the fundamental reference frequency fr and developing required odd harmonic reference frequencies (i.e., 3fr and 5fr) in square wave form. The detector processes the input signal with a VCO for a sine-wave input or a frequency multiplier for an FM input and includes a multiphase clock generator, at least one clock divider (one for each odd harmonic provided for), clock and counter controls, complement gating and two detection counters. Within the detector an increment of resolution is added or subtracted by either or''ing a pulse into the clock stream or by inhibiting a pulse from the clock stream in an operational approach eliminating any requirement for separate harmonic detectors. A small amount of additional gating implements the action of an odd harmonic detector along with gating already present for the fundamental detector.

Automatic traffic controller with plural input receiver circuit

Abstract: An automatic controller system for traffic signal lights comprising a receiver circuit for receiving a plurality of control pulses. A clock generator produces pulse signals exhibiting a particular frequency for enabling the various circuits. A sequencer circuit produces a plurality of output signals representative of a time count for the duration of a complete sequence cycle. A decoder-programmer circuit senses the output signals of the sequencer and generates control signals at preselected time intervals during the sequence cycle to cause sequential operation of said traffic signal lights. Synchronization means are further provided to synchronize each controller cycle at a time determined by the decoder-programmer. The sync. time may be made to occur at any time during the sequence cycle.