Showing papers on "Clock synchronization published in 1982"

Synchronizing Large Systolic Arrays

Abstract: Parallel computing structures consist of many processors operating simultaneously. If a concurrent structure is regular, as in the case of a systolic array. it may be convenient to think of all processors as operating in lock step. This synchronized view, for example, often makes the definition of the structure and its correctness relatively easy to follow. However, large, totally synchronized systems controlled by central clocks are difficult to implement because of the inevitable problem of clock skews and delays. An alternative means of enforcing necessary synchronization is the use of self-timed, asynchronous schemes, at the cost of increased design complexity and hardware cost. Realizing that different circumstances call for different synchronization methods, this paper provides a spectrum of synchronization models; based on the assumptions made for each model, theoretical lower bounds on clock skew are derived, and appropriate or best-possible synchronization schemes for systolic arrays are proposed. In general, this paper represents a first step towards a systematic study of synchronization problems for large systolic arrays. One set of models is based on assumptions that allow the use of a pipelined clocking scheme, where more than one clock event is propagated at a time. In this case, it is shown that even assuming that physical variations along clock lines can produce skews between wires of the same length, any one-dimensional systolic array can be correctly synchronized by a global pipelined clock while enjoying desirable properties such as modularity, expandability and robustness in the synchronization scheme. This result cannot be extended to two-dimensional arrays, however--the paper shows that under this assumption, it is impossible to run a clock such that the maximum clock skew between two communicating cells will be bounded by a constant as systems grow. For such cases or where pipelined clocking is unworkable, a synchronization scheme incorporating both clocked and "asynchronous" elements is proposed.

Local area networks

Abstract: A data transmission network includes a number of access controllers connected to a central hub. The hub includes an arbitrator to select only one access controller for data transmission. Upon selection of one controller all other controllers are disabled to prevent collision of data packets. An interlock prevents enablement of a disabled controller until the data packet received by the transmitter has terminated to prevent transmission of part of a data packet. Synchronization between the data and a master clock is obtained by an initial coarse synchronization and a subsequent fine synchronization. The coarse synchronization is obtained by generation of a number of identical signals with a time delay between each signal. A clock pulse latches to one of the signal paths to provide the initial coarse synchronization.

Process and apparatus for the synchronization on reception of a signal provided with a synchronization pattern

Abstract: A process and apparatus for the synchronization on reception of a signal provided with a synchronization pattern. The process consists of retaining the synchronization setting until it can be readjusted on a periodically appearing potential synchronization pattern, optionally in the absence of a reference synchronization pattern corresponding to a previously acquired synchronization. The apparatus has a potential time base loaded to a given count during the presence of a potential synchronization pattern and a reference time base looped on itself and producing a synchronization signal when it reaches a given count. If a potential synchronization pattern is present in an iterative manner, a logic circuit produces a signal causing the synchronization change by loading the reference time base with the potential time base.

Processor quartz clock synchronisation control - detects time keeping relative to master clock to switch between different quartz circuits

Abstract: The synchronisation control for processor clocks in a decentralised multiprocessor system uses a timing deviation measuring device coupled to the respective processor clock and to the master clock. Its output controls a selection switch allowing one of several alternate quartz circuits with differing frequencies to be coupled to the clock so as to reduce the detected timing deviation. Pref. each quartz circuit is coupled to the selection switch via an oscillation monitor for synchronising the change-over. The synchronisation control is used for clocks incorporated in processors spaced at wide distances.

A proposed study program for the enhancement of performance of clocks in the DCS timing system

Abstract: : Communications System timing survivability can be enhanced by a backup freerunning clock capability, but this requires stable, accurate clocks. Stable, accurate cesium clocks are very expensive. Following a calibration period, errors in less expensive quartz or rubidium clocks can most likely be predicted for a free-running period and removed from sufficient accuracy for an adequate length of time to satisfy many DCS requirements. Use of an Autoregressive Integrated Moving Average (ARIMA) model for this clock error prediction is discussed. (Author)

Process for synchronization on reception of a signal provided with a synchronization pattern

Abstract: A process and apparatus for the synchronization on reception of a signal provided with a synchronization pattern. The process consists of retaining the synchronization setting until it can be readjusted on a periodically appearing potential synchronization pattern, optionally in the absence of a reference synchronization pattern corresponding to a previously acquired synchronization. The apparatus has a potential time base loaded to a given count during the presence of a potential synchronization pattern and a reference time base looped on itself and producing a synchronization signal when it reaches a given count. If a potential synchronization pattern is present in an iterative manner, a logic circuit produces a signal causing the synchronization change by loading the reference time base with the potential time base.

Timing subsystem development: Network synchronization experiments

Abstract: This paper describes a program in which several experimental timing subsystem prototypes were designed, fabricated, and field tested using a small network of troposcatter and microwave digital communication links This equipment was responsible for modem/radio interfacing, time interval measurement, clock adjustment and distribution, synchronization technique, and node to node information exchange Presented are discussions of the design approach, measurement plan, and performance assessment methods Recommendations are made based on the findings of the test program and an evaluation of the design of both the hardware and software elements of the timing subsystem prototypes