Showing papers on "Column (database) published in 1985"

Control and monitoring apparatus for vending machines

Abstract: Sales management data such as sold product number data, sales data, unsold product number data, unit price data and sales condition data of a vending machine and individual columns are stored. When a given column and given sales management data are selected, the given column is displayed on a column display unit, and the sales management data of the given column is displayed on a data display unit. The sales management data can be set or updated. When a failure occurs in the vending machine, a failure position is displayed on the data display unit.

Variable access frame buffer memory

Abstract: A frame buffer memory comprises a set of memory chips arranged in an array of n rows (planes) and m columns. All memory chips are identically addressed, a set of m, n-bit pixels being stored at each memory address with one bit of each pixel being stored in each array plane. Each memory chip of each column is row address strobed by a common row address strobe line while each memory chip of each plane is column address strobed by a common column address strobe line. By appropriately strobing selected row and column address lines, data may be written to the memory array on a pixel-by-pixel or plane-by-plane basis with such data being written to individual pixels or planes or to blocks of pixels or planes. Combinational logic within the frame buffer memory permits pixel data to be rapidly modified according to preselected rules during a memory write operation prior to being written into memory.

Active matrix display device

Abstract: In a thin-type liquid crystal display device of this invention, a display section (10) is formed on a printed circuit board (14) and has a matrix array of display cells (12), address lines (16, 18) connected to the row arrays of the display cells and data lines (20, 22) connected to the column arrays of the display cells Row and column switching selectors (40, 42) are provided on the printed circuit board (14) The respective selectors (40, 42) include a parallel array of switches, such as TFTs The row selector (40) is connected to the address lines (16, 18) for sequentially selecting address lines (16, 18) through a scanning operation for image display The column selector (42) is connected to the data lines (20, 22) for subjecting incoming one image data to a time-division multiplexing and for sequentially supplying block-segmented image data components to the data lines (20, 22)

Method of sequenced braider motion for multi-ply braiding apparatus

Abstract: A braiding method wherein fiber carriers are arranged in rows and columns which are moved in a predetermined alternating sequence to intertwine the fibers and form a braided article. A selected intermediate row is moved a distance sufficient to block movement of a column on one side thereof. While the column is blocked, a tamping force is applied thereto to move it against the one side of the selected row to facilitate proper alignment of the fiber carriers in the column.

Content-addressable memory

Abstract: A content-addressable memory device for searching the address of an input data is disclosed. The content-addressable memory device comprises: memory means including a matrix of memory cells including a plurality of pairs of columns, the row position of each of the memory cells corresponding to the content of the data, the position of each of the pairs of columns corresponding to the address, the first column of each pair of columns being for storing the data at the exact address and the second column of each pair of columns being for storing the data close to the data stored in the first column of the same pair of columns; row selecting means coupled to said memory means and for selecting a row of the memory cell matrix of said memory means corresponding to the input data to be searched. The content-addressable memory device may further comprise: column selecting means for, in response to an input data to be stored in an input address, selecting a pair of columns of the matrix of said memory means corresponding to said input address; and data writing means for writing the input data to be stored in the first column of the pair of columns of said matrix selected by the column selecting means and the data associated to said input data in the second column of the pair of columns selected by the column selecting means, whereby it is possible to store data and it's associated data in the same address so as to carry out search of the associated data at high execution speed.

Programmable pipelined image processor

Abstract: A pipelined image processor selectively interconnects modules in a column of a two-dimensional array to modules of the next column of the array of modules 1,1 through M,N, where M is the number of modules in one dimension and N is the number of modules in the other direction. Each module includes two input selectors (10,11) for A and B inputs, two convolvers (12,13), a binary function operator (15), a neighborhood comparison operator (14) which produces an A output and an output selector (16) which may select as a B output the output of any one of the components in the module, including the A output of the neighborhood comparison operator. Each module may be connected to as many as eight modules in the next column, preferably with the majority always in a different row that is up (or down) in the array for a generally spiral data path around the torus thus formed. The binary function operator (15) is implemented as a look-up table (20) addressed by the most significant 8 bits of each 12-bit argument. The table output includes a function value and the slopes for interpolation of the two arguments by multiplying the 4 least significant bits in multipliers (21) and (22) and adding the products to the function value through adders (23) and (24).

Line selection for preparing range images

Abstract: Selecting of particular image lines for composition of range image such that a composition and evaluation of range image is possible in real time actually corresponds to the imaging of a TV or video camera. The image field is scanned column by column and the contents of the column (all lines) are read in parallel. After digitizing the content of the column, a selection logic selects a particular imaging dot within each of the columns. Using the principles of triangulation, the line position of the dot selected is identified by a multibit binary data word is vertical position in representation of the distance from the camera or the light strip source.

Memory architecture with sub-arrays

Abstract: A static RAM has a plurality of sub-arrays arranged in rows and columns, each sub-array having word lines running the length of the sub-array in a top to bottom direction, and having bit lines running the width of the sub-array in a left to right direction, and having a word line driver for enabling a selected word line in response to receiving a row select signal corresponding to the selected word line; a global row decoder for providing the row select signals as determined by row address signals; a first plurality of column pre-decoders for performing a partial decode of data provided on the bit lines of a first of the rows of sub-arrays, each column pre-decoder corresponding to a particular sub-array; a second plurality of column pre-decoders for performing a partial decode of data provided on the bit lines of a second of the rows of sub-arrays, each column pre-decoder corresponding to a particular sub-array; and a plurality of sense amplifiers for sensing the output of the first and second column decoders. The static RAM has an architecture characterized by the memory having a top side, a bottom side, a left side, and a right side; the rows of sub-arrays running from left to right, and sequentially numbered from left to right with the first column of sub-arrays being nearest the top side; the columns of sub-arrays running from top to bottom, and sequentially numbered from top to bottom with the first row sub-arrays being nearest the left side; and the plurality of sense amplifiers being interposed in the rows of sub-arrays and located between the columns of sub-arrays.

Pixel addressing system

Abstract: Apparatus for identifying a plurality of given elements read out of an array of elements arranged in lines and columns is described. The apparatus includes a line-rate counter for developing addressing signals and a memory for providing data signals corresponding to the column location of the given elements in response to the addressing signals. A programmable counter counts columns in response to the data signals read out of the memory for providing a signal which corresponds in time to read out of respective ones of the plurality of given elements.

Configurable logic array

Abstract: A special interconnect circuit which connects adjacent configurable logic elements (CLEs) in a configurable logic array (CLA) without using the general interconnect structure of the CLA. In one embodiment, an array of CLEs is arranged in rows and columns and a special vertical lead circuit is provided which connects an output lead of a given CLE in a given column to a selected input lead of the CLE above it and below in the same column. Special horizontal lead circuits are provided which connect a given output lead of a given CLE to a selected adjacent input lead of the CLE in the same row.

Video signal memories

Abstract: A video signal memory which may form a field memory in a special effects equipment of a high definition video system, provides storage of n 2 m video data words and includes an array of n by n memory modules each capable of storing m video data words corresponding respectively to sample values at respective sample positions of a raster display, a first group of n buses for supplying data and address signals to the n columns respectively of the array, a second group of n buses for supplying data and address signals to the n rows respectively of the array, and means selectively to enable the first or second group of buses in each write cycle of the video signal memory and in the write cycle to supply over the enabled group of buses up to n data and address signals wherein the address designates the address in a memory module in the corresponding column or row of the array and the data is the data to be stored in the memory module.

Redundant column substitution architecture with improved column access time

Abstract: An apparatus and method for redundant column substitution in a memory device with column redundancy. Rather than inhibiting normal column decoding and selecting in response to a defective column address, the present invention proceeds in parallel with normal column access and redundant column access. The I/O multiplexer receives both the normal and redundant data and, in response to an input from the redundant column decoder, selects the redundant data. Column access time is improved in the case of substituted redundant columns due to the lack of inhibiting the normal column select process. Redundant columns are located physically close to the I/O multiplexer to provide for shorter I/O lines and further improved access time for the redundant columns. Floating normal bit lines are avoided in this scheme since normal column selection is not inhibited.

System and method for orthogonal image transformation

Abstract: A system using a special memory matrix termed an "image prism". The image prism is row and column accessible and is connected to input and output of a conventional bitmap memory. Row select lines pass horizontally through the matrix, column select lines pass vertically through the matrix, data lines run perpendicular to select lines. Row and column data lines are tied together at nodes on a diagonal of the matrix. Data-in lines and data-out lines comprise two sets of data lines. Data words enter the image prism with bits in parallel along the row data-in lines. Data words exit the image prism along the column data-out lines. Data may be written into or out of the image prism by either row or column and either forward or backward. Image data is transformed by transforming image prism size tiles of data using the image prism, and moving them to their final destination in bitmap memory.

Distillation column and process

Abstract: Dual interrelated distillation columns are disclosed wherein the heat from a first column is transferred by thermal conduction through a common wall or surface to a second column to increase efficiency and decrease waste of energy. In one embodiment, the first heat generating column is a cylindrical column, and the second column is an annular column concentric to the first column. This concentric arrangement permits the heat generated in the first column to flow outwardly into the second column, thereby improving its efficiency and reducing the heat loss. Typically, the inner first column is a high pressure rectifying column, and the outer concentric column is a stripping column. In an alternate embodiment, the inner column can simply be a portion of a high pressure distillation process, and the outer column is a portion of a lower pressure distillation column. In alternate embodiments, the rectifying apparatus can assume a variety of shapes such as a plurality of packed tubes which extend through the stripping column or a corrugated configuration or rectangular configuration as desired.

Single-ended sense amplifier for dynamic memory array

Abstract: A semiconductor memory device having an array of rows and columns of dynamic one-transistor memory cells uses a single-ended differential sense amplifier connected to each whole column line, rather than separately to column line halves. A bistable circuit with cross-coupled driver transistors has one side connected to the column line by a first coupling transistor which turns off as the row line goes high to trap a fixed reference voltage, then the other side is connected to the column line by a second coupling transistor which turns on after the column line has settled out. This column line voltage is related to whether a 1 or 0 is stored. The time needed to precharge the column line is short because two halves need not be precharged from different levels, and so the memory cycle time is short. Also, the device is less susceptible to errors due to alpha particles because a change of the bit line voltage equally effects both inputs to a sense amplifier.

Multirelations: semantice and languages

Abstract: We argue that a multirelation (relation with duplicates) is not, a semantically independent data object, but rather it should be viewed as a sub- set of columns within a larger relation that has no duplicates. Consequently, at the level of the con- ceptual database, duplicates in base relations or in views are not allowed, nor are operations on mul- tirelations. Multirelations as query output can be specified by designating a subset of some relation's columns for output, while "hiding" the rest of the columns. Similarly, aggregate functions are applied to multirelations by applying them to a column within a relation. Our approach can be applied to extend any query language in a consistent way to have full multirelational expressiveness, and such an extension for the query language QUEL is detailed.

Non-volatile semiconductor memory

Abstract: PURPOSE:To enable sufficient functional test and high reliability at low cost by arranging cells for the first test in the column selector side of each column line, and cells for the second test in a row decoder of each row alternately one at the nearest position and the fastest position, and placing at least one in each column line. CONSTITUTION:In the case where test is started and a test row decoder 12 is selected, a main row decoder 3 becomes non-selection and test on writing and reading to cells 11 for first test connected to each column line is performed by a column selector 5. When selecting a column selector 14 for test, a main column selector 5 becomes non-selection, and test on writing and reading to cells 13 for second test connected to each row is performed by a row decoder 3. Cells 11 for first test connected to each column line by a row decoder 12 for test are arranged at nearest position and farthest position from the main column selector 5 alternately in each column line. Accordingly, a delay test of speed due to stray capacity, resistance etc. of column line can also be executed, and a function test of memory cell and AC characteristic is also able to be executed.

Transformation Matrices in Input—Output Compilation

Abstract: Within the framework of the United Nations’ “System of National Accounts” (SNA)1 proposals are made for integrating input-output tables in national accounting. According to the SNA, input-output tables with uniform column and row classifications should not be calculated directly, but input-output compilation should start with computing two basic table swith different column and row classifications. One of these tables, the output table, shows the output in a breakdown by industry (producers) and commodity group. The output table is also called the make matrix. The other table, the input table, shows the intermediate use of the commodities by industry (users) and commodity group (use matrix), the final uses by commodity group and the gross value added by industry. Under the aspect of data availability, these tables are the best presentation scheme for input-output figures. In a second step, the basic tables are transformed to input-output tables with uniform row and column classifications (commodity x commodity or industry x industry tables). These tables are used for input-output analysis.

Sanitary facility with means for automatic cleaning

Abstract: An automatic sanitary facility for public or private use which comprises a service column connected to the electrical and hydraulic network and connectable to one or more toilet compartments, each provided with a floor-level or cup-shaped toilet bowl, the service column being equipped with automatic means for control and for hydraulic and mechanical cleaning, each of the mentioned bowls being transferable by means of an actuator to the inside of the service column for cleaning operations.

Extendable directional dipole antenna

Abstract: The invention pertains to an extendable directionally adjusted dipole antenna particularly suitable for use with recreational vehicles. The antenna includes a vertical column having an extendable dipole arrangement at its upper end utilizing flexible actuators associated with a pair of reels whereby the actuators and associated telescoping antenna assemblies are simultaneously extended and retracted. An operating shaft for rotating the reels extends through the column and either manual or electric means rotate the shaft. The column is rotatable for directional adjustment, and under manual control the shaft extends through the vehicle roof permitting interior adjustments.

CMOS ROM Data select circuit

Abstract: © A data select circuit for selecting a column line in a CMOS ROM and for establishing a connection between a pair of bit lines and corresponding data lines uses a single NMOS pull-down transistor on the column line and a pair of P-channel pass transistors on the bit lines, the pass transistor gates being controlled not by an inverted column decode line, but by the column line itself, thus reducing the capaca- tive load on the column decoder and saving space.

Problem solving game

Abstract: A game in which players gain points by correctly solving problems depicted on cards in a chart-like format The cards are divided into three cards sets according to three different levels of difficulty Six vertical columns each having a plurality of slots for receiving chips are used for keeping track of each player's score Each player is assigned a vertical column The six vertical columns are each divided into three areas corresponding to the three card sets Players progress during the game by correctly solving problems and inserting chips The card set from which a players must choose a card is determined by the column area the player has progressed to The first player to earn a predetermined number of points wins the game The solution to each problem and clues to aid in solving each problem are provided

Data imprinting device

Abstract: PURPOSE:To imprint data without providing a data imprinting device by positioning the potential detection part of a photosensitive drum at an image exposure position, and composing an eraser of a writable light emitting element array. CONSTITUTION:The measurement of the surface potential of a photosensitive drum 1 and the imprinting of data differ in operation timing, so a surface potential measuring device is used even for the data imprinting operation in common. A data imprinting device 17 consists of an interimage eraser unit 200, optical path shutter 210, surface potential sensor 211, eraser 220 for a surface potential detection part, etc. Then, LEDs 200a-200e of the interimage eraser unit 200 are turned off in data imprinting mode and the data imprinted part of the photosensitive drum 1 is not erased. The seven LEDs 220a-220g of said eraser 220 constitute a column of a dot matrix of five rows and seven columns of dots. There is no probelm in terms of space, so data is imprinted at low cost even by a small-sized copying machine.

Method for selective menu display based on password

Abstract: PURPOSE:To protect the security of menu display in a work station by selecting menu display on the basis of a password in accordance with an operator. CONSTITUTION:A list of program numbers and program titles fed to individual application programs 2-6 is stored in a menu table 8. Passwords are assigned to persons who are permitted to operate this system, and passwords are inputted when the system is started. A password correspondence table 9 indicates application programs which individual operators are permitted to use, and a menu flag is set at the intersection between a row of the password of a pertinent operator and a column of the application program, which he can use, out of intersections between rows of passwords fed to individual operators and columns corresponding to individual application programs. Thus, the security is protected.

Insertion printer for table data

Abstract: PURPOSE:To perform insertion printing of table data without forming table data having character rows to be insertion-printed which correspond to insertion printing designating codes, by a method wherein the contents of insertion printing data are designated by using a row number and/or a column number of table data. CONSTITUTION:A document constituted of character rows 81, 82, 83 and the character rows 86, 87 to be insertion-printed is printed on the basis of a document data constituted of table data designated as an object of insertion printing, the character rows 81, 82, 83 and the insertion printing designating codes 84, 85. The codes 84, 85 are constituted of insertion printing marks 84a, 85a indicative of insertion printing and the column numbers and/or row numbers 84b, 85b of the table data as keywords for retrieving the data to be insertion-printed from the table data.

Internally synchronous matrix structure for use in externally asynchronous programmable devices

Abstract: The speed of operation of a programmable logic device which contains internally synchronous circuit structure is increased by an improved architecture which does not require a power-up transition cycle Synchronous operation is carried out only for one transition In each column of the matrix of programmable cells, the rows of which are coupled to receive the logic signals upon which the device is to operate, the programmable cells of that column are coupled via a respective inverter feedback pair to a column output link of the matrix The connection between the programmable cells of the matrix and the inverter feedback pairs are coupled to pull-down switch devices control inputs of which are coupled to the output of an OR tie, inputs or which depend upon a prescribed transition on row input links This transition is detected by respective transition detectors which trigger only on a particular transition edge When the row inputs to the matrix change state, the column outputs follow the transitions asynchronously, with the only delay being that imparted by the inherent delay through the inverter feedback pairs When the row inputs switch or transition to the opposite state, the transition detector of each row provides an output which, through the OR tie, triggers the pull-down switches These pull-down switches are capable of overriding the feedback inverter pair to force the column low if it had previously been high and if no other row is holding the column high For this transition, the matrix operates synchronously

Line state supervisory system of communication device

Abstract: PURPOSE:To forecast the state of communication to each address at each time zone by storing the communication state based on the result of communication depending on the time of a time management means every time the control means makes a call. CONSTITUTION:A file 1 consists of an address column 10, a transmission mode column 11, and communication state columns 12-1n, address names A-N are described in the address column 10 and the transmission mode (GII, GIII) of each address is described in the transmission mode column 11. The communication state columns 12-1n are divided at each time zone and each column is divided into a busy column 12a representing whether or not the communication state is busy and a communication speed column 12b. The busy column 12a is provided with a career column storing the call state for 10 calls at maximum and a statistic column for career and the state by majority decision is stored in the statistic column. The communication speed column 12a is provided with the career column storing the communication speed of maximum 10 calls as the career and with the statistic column and they are updated at each call.

U-Optimum row-columns designs for the comparison of two treatments

Abstract: AllU-optimumu x v designs for the comparison of two treatments are to be characterized here — the row and column figuresu andv being arbitrary.