Showing papers on "Effective number of bits published in 1973"

Data display system having a multilevel video storage device

Abstract: A radar return signal is analyzed by amplitude comparators so as to classify the radar return signal with respect to 2n -1 threshold levels to thus produce n parallel bits for each classification defining the instantaneous amplitude of the radar return signal. The bits in a given significant bit position (most significant, least significant, etc.) comprise a word which moves through the video storage device serially with respect to bits in the same significant bit position and in parallel with respect to bits in the word comprised of different significance bits. Input buffers in the form of n storage registers are provided, each storage register being associated with a particular bit significance. The bits are entered into their associated storage register at a rate dependent upon the desired radar range. The bits are optionally integrated on a bit-by-bit basis and then entered into a main memory having n circulating storage registers arranged in parallel. The information stored in the main memory is subsequently recalled and conveyed through output buffers for display on a cathode ray tube. The output buffers are comprised of n further storage registers. Each of these further storage registers is associated with a particular circulating storage register. The bits from a circulating storage register are conveyed to its associated further storage register. The bits in the output buffers are subsequently passed into a digital to analog converter, the output of the converter being applied to the cathode ray tube for display.

Multi-level error detection code

Abstract: An error detecting coding and decoding system employing an encoder having a plurality of shift register systems for generating independent sequences of check bits for multiple level checks. A decoder having similar shift registers is employed to regenerate the check bits from the transmitted information and to compare the locally generated check bits with the transmitted check bits generated by the encoder.

Random error correcting system

Abstract: A rate one half random error correcting convolutional coding system capable of correctng two out of any twelve information and parity bits having an encoder comprising a six stage shift register and a modulo 2 adder connected to the shift register for combining the first, fourth, fifth and sixth information bits present in the register to generate parity bits which are subsequently interleaved with the information bits. A decoder employing another six stage shift register generates syndrom bits by combining parity bits generated from the received information with the received parity bits. The syndrome bits are applied to a six stage syndrome register which is coupled, both directly and via other modulo 2 adder, to a majority logic circuit which provides a correcting signal when the number of ones applied thereto exceeds a predetermined number.

Digital data compression method and system

Abstract: A data compression method and system for logarithmically compressing a digital data signal is disclosed. A digital signal related to the number of successive binary bits of one signal level in the digital data signal is generated by counting the number of successive bits of the one level in the order of decreasing significance of the bits of the digital data signal. The digital signal is then combined with a predetermined number of the uncounted bits of the digital data signal to provide a compressed data signal having fewer bits than the original digital data signal. The digital signal is preferably generated by entering the digital data signal into a serial shift register and monitoring the stage of the shift register initially containing the most significant bit. The digital data signal is then shifted through the shift register in a direction tending to shift each bit into the monitored stage and the number of shifts is counted by a binary counter. The counter is inhibited when a predetermined binary level is detected in the monitored stage of the shift register and the count in the counter is combined with a predetermined number of the bits remaining in the shift register to form the compressed data signal.

Analogue-to-digital convertors

Abstract: An analog-to-digital converter comprises a series connected chain of encoder bits adapted to provide a digital output signal indicative of the amplitude of an applied sampled analog signal. A plurality of storage elements are connected respectively to the outputs of said encoder bits to receive the signals therefrom in response to a triggering signal from a triggering source. Delay elements are provided to delay progressively the storage of the output signal from respective ones of said encoder bits to compensate for propagation delay in the chain to effect storage of a digital signal indicative of an instantaneous level of the analog signal.

A Generalized Cellular Array for Digital Communication

Abstract: Satellite communication essentially needs ultrareliable, compact and fast electronic systems. For reliability digital communication is extensively used in space and satellite communications. In digital communication the analogue message, to be transmitted, is digitally encoded by an Analogue-to-Digital converter. The bits of digitally encoded message are known as information bits. Then before transmission, a number of ‘redundant’ bits is appended to the information bits for error detecting and correcting at the receiving end. The generation of these redundant bits is usually done sequentially by shift registers and logic gates. Such methods are time-consuming and hence uneconomic for space communication. Recently, methods have been developed whereby a large number of logic elements can be fabricated on a single chip of substrate. These ‘large scale integrated’ arrays are very fast, compact and cheap. Iterative and ‘cellular’ organization concept is particularly useful in such systems. In this paper the ap...