Showing papers on "Emulation published in 1983"

Measurement of fault latency in a digital avionic mini processor, part 2

Abstract: The results of fault injection experiments utilizing a gate-level emulation of the central processor unit of the Bendix BDX-930 digital computer are described. Several earlier programs were reprogrammed, expanding the instruction set to capitalize on the full power of the BDX-930 computer. As a final demonstration of fault coverage an extensive, 3-axis, high performance flght control computation was added. The stages in the development of a CPU self-test program emphasizing the relationship between fault coverage, speed, and quantity of instructions were demonstrated.

Microcomputer communications software

Abstract: Disclosed is a microcomputer communications software implementation for controlling the transfer of data between a microcomputer and a host mainframe computer in various modes of operation, including an unattended mode, a terminal emulation mode, an automatic mode, and a manual mode. The present invention is particularly suitable for use with cash management systems.

Digital Light Box, One Of The Integral Pieces Of PACS

Abstract: A workable PACS system consists of several discrete assemblies which are linked together by data communication links for terminal and image data input and output. Two phases of development of a PACS system can be identified and labeled: emulation and enhancement. The latter is characterized by the observation "you do that so well, can you also do this?" Emulation, on the other hand, assures an accepted and working system. One of the key components of a PACS system is the emulation of the classical and ubiquitous "lightbox". This paper presents an emulation of the lightbox using a highspeed digital disk and video display on multiple high resolution monitors capable of 1024 x 1024 or 512 x 512 resolution pixel display. The emulation features are: a) loading and reloading in less than one second, b) access to between 800 and 3200 digital radiographs, and c) highspeed review forward and backward through this list of radiographs at rates up to 30 new images/second. Operation is under manual control both in rate and direction. This stresses the speed. The feature which makes this "lightbox" emulation desirable is the ability to dwell on a presently viewable display of digital radiographs with access to previous and following images in the study. One of the features desired in an emulation is that the components be "off the shelf". This means that existing hardware is used in the emulation. Software can then be generated based on known hardware. The emulation has flexibility of size: multi-image displays ranging from 2 or 3 images side by side to the piano-roll type endless display of an array with 4 images side-by-side and 3 rows visible at any one time. In addition, it has flexibility of resolution: radiographs displayable within a 256 x 256 pixel region to those displayable within a 1024 x 1024 pixel array as well as images which are much larger (4000 pixel by 4000 line chest radiograph scans) using a 1024 pixel by 1024 line window into the radiograph. The emulation of the "lightbox" finds application at both radiology review stations and at locations for consultation with attending physicians.© (1983) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

A multiprocessor emulation facility

Abstract: Interest in multiprocessor computer architectures has increased dramatically in the last ten years. However, it has become clear that, in order to effectively use multiprocessors in a general way, some fundamental changes in the model of computation are necessary. Moreover, experimentation in the field is hindered by low-performance simulation tools and high-cost hardware modeling schemes. We present our approach to solving both of these problems: Dataflow Architecture, which provides an inherently parallel model of computation, and a Multiprocessor Emulation Facility, which is a general purpose tool for evaluating multiprocessor architectures at low cost. We also discuss our scheme for using the Emulation Facility to validate our claims about dataflow architecture.

Interleaved processing of non-numerical data stored on a cyclic memory.

Abstract: The memory access delay, caused by the ’emulation’ of the random access capabilities on a sequential access memory type, is stated as a problem in Non-Numerical Data Processing and the motivation f ...

The microcomputer as a training aid for online searching

Abstract: A training package has been developed at the College of Librarianship Wales for online searchers. It operates on a microcomputer and comprises a series of CAL questionnaires and a Dialog emulation. The advantages and disadvantages of such packages for teaching are discussed.

Emulation and Replication as a Scenario for Successful School Improvement.

Abstract: DOCUMENT RESUME

Performance analysis of multiprocessor based control systems

Abstract: Previous work on multiprocessor performance evaluation has focused on Markovian models. It is shown that for control system design another performance modelling approach is required. A worst-case design methodology is necessary to avoid fatal behaviour. Timing constraints are specified which must be satisfied to obtain valid results prior to cyclic deadlines. Emulation of the control system on the CM multiprocessor is used to validate the results of the analytic performance evaluation. 6 references.

Traffic Service Position System No. 1B: System description

Abstract: The Traffic Service Position System No. 1B (TSPS No. 1B) is the first field application of the Bell System's new 3B20 Duplex Processor (3B20D) in the emulation mode. The 3B20D Processor replaces the existing Stored Program Control No. 1A (SPC 1A), while retaining the existing TSPS periphery and software. A key factor is the ability to switch between the emulated software and the 3B20D native software within a single process with a single instruction. This allows the flexibility of adding software in either environment as appropriate.

Digital Emulation of Analog Computer Techniques for the Solution of Kinetic Systems

Abstract: A low-cost microcomputer and package of assembly language routines has been developed to emulate the structure and performance of a large analog computer. The advantages of the analog computer, as implemented in this scheme, include (1) a significant reduction in the programming effort involved in modeling complex dynamic systems and (2) the control of the simulation and model parameters in a completely interactive and flexible manner. The symbolic nomenclature and schematic representations involving devices, such as integrators, comparators, multipliers, and function generators, offers a powerful alternative to the more conventional numerical methods, that is, to provide very simply the solutions to large systems of differential equations. This approach invariably leads the user to a more thorough understanding of the dynamic character of the system. The technique is illustrated using a chemical kinetics example involving the simulation of laser-induced fluorescence. The results of this work have provided an assessment of a systematic error that occurs when using induced resonance fluorescence to measure OH concentrations in the troposphere of the earth.

Emunet “emulator of network systems” a general framework

Abstract: The project discussed here provides a general tool, the architecture of which allows to emulate various network configurations, and to implement various synchronization algorithms for distributed control, distributed data or functions. This emulation enables the measurement of various characteristics of these algorithms: resiliency, overhead, fairness, response time and so on. This tool resides in a physically local network, built with homogeneous microcomputers. The desired network is simulated on this physical network. The topology of the physical network supporting the simulation is a star. The central node is considered from the other satellite computers as a simple transport medium which emulates the links of the required network to which each one is connected. In the central node a simple interpreter performs the desired emulated network (loop, mutidrop, mesh….) by consulting a description of the links of this network. The simulation is made, using 3 layers of software in the central node emulator: first level: connections with the various computers of the physical network and data link control protocols. second level: path control where the routing of the various messages is performed between the satellites in the simulation. third level: traffic supervision, keeping track of the different transactions and to develop measurements and statistics on the running of the simulated network. In the satellites, the distributed systems and applications are implemented. This tool is intended to facilitate the implementation and the testing of algorithms for distributed control as well as algorithms for distributed data: ticketing algorithms, virtual rings, logical clocks or any other. Even more, it is designed to measure the different characteristics of these algorithms so as to permit their comparison. Its modularity authorizes also to perform the simulation of various faults in the satellites.

Stanford emulation laboratory

Abstract: Over the past decade we have built a laboratory and research environment for the study of architectures and emulation. Initially most effort was directed at building the host processor, EMMY, and its support tools. The next stage was to emulate a variety of instruction sets --- building an archive of emulators. Now we have well over a dozen emulators and can add a new one quickly. A student can emulate a know image architecture in about ten weeks --- twenty weeks includes verification and documentation --- thirty weeks for I/O and interface to a simple operating system. (A student-week is about 6 - 8 hours of effort and corresponds to three units of credit.)

Validation methods for flight crucial systems

Abstract: Research to develop techniques that can aid in determining the reliability and performance of digital electronic fault-tolerant systems, that have probability of catastrophic system failure on the order of 10 to the -9th at 10 hours, is reviewed. The computer-aided reliability estimation program (CARE III) provides general-purpose reliability analysis and a design tool for fault-tolerant systems; large reduction of state size; and a fault-handling model based on probabilistic description of detection, isolation, and recovery mechanisms. The application of design proof techniques as part of the design and development of the software implemented fault-tolerance computer is mentioned. Emulation techniques and experimental procedures are verified using specimens of fault-tolerant computers and the capabilities of the validation research laboratory, AIRLAB.