Showing papers on "Emulation published in 1984"

Emulation of a data processing system

Abstract: Emulation method and apparatus allowing a first system, which is not designed as a functional duplicate of a second system, to emulate the second system. The input/output structure of the second system is emulated in the first system by means of routines stored therein and which direct the already existing input/output structure to operate in the same manner as the input/output structure of the second system. The emulation routines are in turn invoked through the non-maskable interrupt mechanism of the first system by a modification thereto which detects the occurrence of "foreign" input/output requests; that is, input/output requests occuring in programs originally written for the second system and which are not normally recognized by the first system. The means for detecting foreign input/output requests includes means for comparing input/output request port addresses to the range of port addresses occupied by the system input/output devices and indicating when a port address is within the range of address space occupied by the system input/output devices. The foreign request detection means generates a non-maskable interrupt to invoke an input/output emulation routine upon the occurrence of input/output requests which do not normally fall within the range of input/output ports supported by the first system.

Power semiconductor device with main current section and emulation current section

Abstract: A power semiconductor device incorporates in its active, or current-carrying, region a main current section and an emulation current section. The active region is surrounded by a common device termination region. This is accomplished through provision of respective separate cathodes for the main and emulation current regions, while the device anode is common to both the main and emulation current sections. The current level in the emulation current section provides an accurate representation of the current level in the main current section since the main and emulation current sections are closely coupled both thermally and electrically and, further, are formed in the same fabrication process. The current level in the main current section can be economically determined with low power circuitry by way of sensing the current level in the emulation current section.

Cognitive emulation in expert system design

Abstract: Cognitive emulation is an expert System design strategy which attempts to model System performance on human (expert) thinking. Arguments for and against cognitive emulation are reviewed. A major conclusion is that a significant degree of cognitive emulation is an inherent feature of design, but that an unselective application of the strategy is both unrealistic and undesirable. Pragmatic considerations which limit or facilitate the viability of a cognitive emulation approach are discussed. Particular attention is given to the conflict between cognitive emulation and established knowledge engineering objectives, detailed over 12 typical expert System features. The paper suggests circum-stances in which a strategy of cognitive emulation is useful.

Emulation as a design tool in the development of real-time control systems

Abstract: A major facility for manufacturing research is being established at the National Bureau of Standards. The Automated Manufacturing Research Facility (AMRF) will provide testbed where measurement research of computer integrated manufacturing systems can be performed. The control architecture of the facility is based on a sensory-interactive, modular, hierarchical, feedback system. Each module is represented as a finite state machine that interacts through a shared time-sliced common-memory where command, feedback and database information is stored.A hierarchical control system emulator (HCSE) has been developed that allows the system to be designed and tested before implementation on the actual hardware. The HCSE has been successfully used in the AMRF project as a design management tool, providing a complete specification of the control software. It is also used as a testing aid that allows a given module (i.e., a robot control system) to interact with emulated control modules substituting for unavailable AMRF hardware.

A Flexible GPS Software Development System and Timing Analyzer for Present and Future Microprocessors

Abstract: Discussed is a timing emulation and operating system which predicts loading for microprocessors and enables efficient generation of software found in such applications as the Global Positioning System The timing emulator is applied to two classes of user equipment, a conventional fast-multiplexed design and a fully integrated processor featuring continuous state feedback into the spread-spectrum demodulation and tracking loops Timing data are developed for five representative microprocessors ranging from 818 to 32132 register/bus widths The advanced integrated processor requires augmentation of the 32132 processor with a math co-processor The emulator is used to develop speed requirements on the co-processor Lastly, the software development system is described This contains a multi-tasking operating system and matrix library written in the language “C” which may be easily adapted to a range of radio-navigation problems

A multitasking implementation of system simulation: The emulation of an asynchronous parallel processor for system simulation using a single processor

Abstract: This paper describes the design and the development of a multitasking implementation of system simulation for the purpose of emulating an asynchronous parallel processor for system simulation using a single processor. The multitasking simulation system is a FORTRAN software kernel built around an existing simulation language (GASPIV) so that it emulates an asynchronous parallel processor simulation system. The multitasking simulation system is in full operation on a Texas Instruments 990/12 minicomputer and it is being used successfully to emulate the software architecture of the parallel processor simulation system being designed and built in the Industrial Automation Laboratory at Texas A & M University.

UPEML: a machine-portable CDC Update emulator

Abstract: UPEML is a machine-portable CDC Update emulation program. UPEML is written in ANSI standard Fortran-77 and is relatively simple and compact. It is capable of emulating a significant subset of the standard CDC Update functions including program library creation and subsequent modification. Machine-portability is an essential attribute of UPEML. It was written primarily to facilitate the use of CDC-based scientific packages on alternate computer systems such as the VAX 11/780 and the IBM 3081.

Parallel processor engine model program

Abstract: The Parallel Processor Engine Model Program is a generalized engineering tool intended to aid in the design of parallel processing real-time simulations of turbofan engines. It is written in the FORTRAN programming language and executes as a subset of the SOAPP simulation system. Input/output and execution control are provided by SOAPP; however, the analysis, emulation and simulation functions are completely self-contained. A framework in which a wide variety of parallel processing architectures could be evaluated and tools with which the parallel implementation of a real-time simulation technique could be assessed are provided.

Emulation control system of program

Abstract: PURPOSE:To perform a high-speed and high-execution performance emulation control, by providing an execution control instruction, which emulates the instruction of another system, in an emulator in plural computer systems different in machine language instruction. CONSTITUTION:By the start request of a processing program 11, an emulator 14 sets an execution start address 19 of the program 11 to an instruction counter area IC of an operand table 17. Next, an execution control instruction (EXECUTE) 20 of the emulator 14 is executed, and an instruction processor 12 is operated, and the instruction processing is started from the address 19 of the program 11. Hereafter, processings of instructions other than a supervisor call (SVC) instruction 13 of the program 11 are performed by the processor 12. The execution control instruction which emulates instructions of another system is provided in this manner to perform a high-speed and high-execution performance emulation control.

Pseudo-emulation facilities for the ferranti FDS-10 development system

Abstract: The absence of in-circuit emulation facilities on the Ferranti FDS-10 microprocessor development system may force unacceptable restrictions on the development of hardware and software for an FlOO-L-based project. The disadvantages of this lack of support are discussed and a solution is presented, in the form of a pseudo-emulation facility, which provides many of the features normally associated with in-circuit emulation. Development of a special-purpose interface circuit, allowing communication between the FDS-10 and the target hardware and software, is described and details are given of the monitor program which runs in the FDS-10 and which controls the hardware via the interface.

Data processing device

Abstract: PURPOSE:To make an integrated emulation possible and to process instructions of a target machine in a high speed in the emulation state by executing plural programs different in instruction word system in time division. CONSTITUTION:In case of transfer from the native state to the emulation state, an interface program is read out from a main storage MM, and an execute local EXL instruction in this program is set to a register 11. A control signal is transmitted to an updating circuit 17 through a decoding circuit 12 and a selecting circuit 15, and the control is branched to a program which should be emulated and is stored in a table of the main storage MM. Simultaneously, an address of switching to emulation is set to a program counter 18 from the selecting circuit 15. The instruction read out from a control storage 19 is decoded to generate a control signal for state control bit, and a state control bit register 14 is turned on from the turning-off state by this signal.