Showing papers on "Fault coverage published in 1973"

A Formal Methodology for Fault Tree Construction

Abstract: A model is presented for formulating the Boolean failure logic, cailed the fault tree, for electrical systems from associated schematic diagrams and system-independent component information. The model is developed in detail for electrical systems, while its implication and terminology extend to all fault tree construction. The methodology is verified as formal by fault trees constructed by a computer with typical execution times for a fault tree with 100 gates on the order of 7 sec (on the UNIVAC 1108 computer). The model, called Synthetic Tree Model, is a synthesis technique for piecing together, with proper editing, a fault tree from system-independent component information beginnlng with the main failure of interest and proceeding to more basic failures. The resultant fault trees are in conventional format, use conventional symbols, and are, consequently, immediately compatible with existing solutions techniques. While Synthetic Tree Model develops the fault tree to the level of primary failures, extensions of the model could handle secondary failures, i.e., failure- related feedback between components. ( auth)

Fault diagnosis using time domain measurements

Abstract: A voting technique is used to diagnose fault conditions down to component level in a feedback control system using only the input-output cross-correlation function measured at suitable time delays. These time delays are chosen using a new formula based on Bayes's theorem, which ranks the time delays in order of usefulness in fault diagnosis; it can be readily applied at the design stage, thus assisting the integration of system design and test functions. The fault conditions necessary to set up the scheme may be obtained by direct fault generation in an actual system, or by simulation of the system mathematical model. A learning approach to the design of a fault diagnosis scheme is described which makes full use of any available failure data, together with the ranking formula for time delay selection, in the creation of an optimum scheme.Results obtained on a complex electro-hydraulic servo are presented which show that the scheme works satisfactorily in the presence of measurement noise and parameter drift, two factors which often cause a breakdown in conventional pattern recognition techniques. The computational requirements are extremely modest, and are well within the capacity of present day mini-computers proposed for use in automatic test equipment. In many instances, the scheme is suitable for manual and partially automated test sets, and can be used for fault diagnosis of a wide range of circuits and systems.

Use of SPOOF's in the Analysis of Faulty Logic Networks

Abstract: In general, one cannot predict the effects of possible failures on the functional characteristics of a logic network without knowlegde of the structure of that network.

Test point placement to simplify fault detection.

Abstract: The problem of selecting test points to reduce the number of tests for fault detection in combinational logic networks is examined. A method is presented for labeling the lines of a network. Procedures are described for obtaining a minimal labeling, i.e., one corresponding to a minimal set of tests, for fanout-free circuits and for a restricted class of circuits with fanout. Using these procedures, a branch-and-bound algorithm is developed for selecting an optimal (or near-optimal) set of q test points in fanout-free networks. Some difficulties associated with test point placement in general networks are pointed out. It is shown that the labeling approach is also applicable to the problem of selecting and placing control logic.

A fault tolerant multiprocessor architecture for real-time control applications

Abstract: This paper presents a fault tolerant multiprocessor architecture suitable for real time control applications requiring an extremely high degree of reliability. The architecture satisfies the following requirements: l) Ability to deal with software as well as hardware faults: The proposed architecture is based on the assignment of distinct but redundant software modules to each task. 2) Efficient use of resources: The proposed architecture is a multiprocessor using time redundancy for fault correction. Thus, redundancy (beyond that needed for fault detection) is invoked only when a fault is detected. In normal operation, this extra capacity is available as an additional computing resource. 3) No hard core: In addition to the usual replication of system components, a partitioned system executive and a unique communication facility is defined which insures that the available redundancy will not be lost through a “domino” effect. 4) Interaction of computing units with sensors and effectors: The manner in which system architecture must be responsive to the amount and type of redundancy provided by the sensors and effectors is shown. 5) Use of current technology: The proposed architecture is based on the use of currently available hardware for the major system components. After a detailed description of the architecture and the method of system operation, the system is related to existing fault tolerant systems, and unique characteristics of the present design are indicated.