Showing papers on "FLOPS published in 2015"

SX-ACE, the Brand-New Vector Supercomputer for Higher Sustained Performance II

Abstract: This paper describes an introduction of NEC’s brand-new vector supercomputer, SX-ACE. The SX-ACE, which inherits and improves the NEC’s SX vector architecture, is developed to provide superior sustained performance, especially for memory-intensive applications. For this purpose, the SX-ACE processor achieves the world’s top-class single core performance of 64 GFLOPS and the world’s leading memory bandwidth of 64 GB/s per core. Moreover, the SX-ACE system is designed to reduce power consumption to one-tenth with just one-fifth the floor space as compared to the previous SX-9 model by maintaining the same system performance. In this paper, we elaborate on the design concept, architectural overview, and implementation of the SX-ACE. We also discuss the sustained performance of the SX-ACE for several benchmark codes. The evaluation results demonstrate significantly improved sustained performance and power efficiency of the SX-ACE system in comparison with the SX-9.

The Way the HPC Works in CFD

Abstract: Rapid growth in the capability of single-processor computers has slowed in recent years. It is now evident that further increases in speed require multiple processors. The advantage of high-performance computing over classical vector supercomputers is scalability. The computers also use standard chips and are therefore cheaper to produce. Commercially available parallel computers may have thousands of processors, terabytes of memory, and computing power able to perform one quadrillion floating point operations per second. However, it is a fact that computational fluid dynamic (CFD) algorithms designed for traditional serial machines may not run efficiently on parallel computers. This chapter focuses on how CFD can be used in parallel and on parallel architectures.

Case study of explicit and implicit pulsed flip flops with conditional pulse enhancement mechanism

Abstract: In this paper a study of power efficient pulse triggered flip flops was conducted by adopting a pulse control scheme (PCS), named conditional pulse enhancement. The conditional pulse enhancement scheme consists of a simple pass transistor ‘AND’ gate design and a pull up ‘pMOS’. This set up reduces circuit complexity and removes the pulse generation control logic from the critical path, which facilitate a faster discharge operation as well as improvise the discharge speed conditionally. In this project, the effect of conditional pulse enhancement scheme on the power as well as performance of conventional flip flop such as ep-DCO, ep-CDFF, ip-DCO, are analyzed. The performance analysis was carried out by adopting 180nm CMOS technology. The simulation results reveal that implicit flip flops with conditional pulse enhancement scheme outperforms the conventional flip flops in terms of power and timing characteristics.

Comparative analysis of power in Adder using single bit and multi-bit fip-flops, controlled by dynamic hardware control circuit

Abstract: Any design in VLSI is considered, in terms of area, Speed and Power. The factors interrelated with the above three major factors are Delay, Placement, & Skew. Out of these Delay and Skew are the main timing constraints which have to be considered in VLSI design. Power is a main factor because, an increase in it increases cost in terms of heat sink and hardware required for cooling. In VLSI Flip flops are the majorly clock depended, because their output is dependent on the application of clock pulse, and clock pulse causes the switching of the logic circuits and hence the clock power is of major concern. We get a considerable reduction in power if we reduce the factors which cause power consumption. Multi bit flip flops have been used with this point of view. All the work related to multi bit flip flop has been don at post placement level. In this paper we are focusing multi bit flip-flops at design phase. Considerable work is possible if utilization of flip flops is done properly. We have focused on the application of multi bit flip flop in Adder application and thereby its effect on power, delay and skew. A combination table is built and a dynamic hardware control circuit has been used which will control the utilization of flip flops and only use those flip flops which are needed, depending on the number of bit at the output.