Showing papers on "Frequency counter published in 1981"

Dual frequency radar receiver

Abstract: A radar receiver for detecting quasi-harmonically related radar signals includes an antenna system (10) having a mixer (15) included therein. One harmonic from a local oscillator (20) mixes with a signal at a first frequency to produce an intermediate frequency, and another harmonic of the local oscillator mixes with an input signal at a second frequency also to produce an intermediate frequency. A second mixer (30) and local oscillator (40) may be provided. A bandwidth limited signal detecting system preferably includes a band pass filter (50), a limiting IF amplifier (55) and a frequency discriminator (60). The frequency of either the first or second local oscillator is repeatedly varied by a sweep generator (35) to insure that the presence of a radar signal will pass through the band pass filter (50) and be detected. A low pass filter (65) reduces the noise component output of the discriminator, and a comparator (70) provides output pulses whenever a radar signal within either of the quasi-harmonically related frequency ranges is detected. Radar signals at the two frequencies can be distinguished from each other by the time between the pulses generated as detected by a circuit including a one-shot (110), a counter (120), a clock (115), gates (125, 130, 135, 140), and indicators (145, 150).

Digital frequency divider suitable for a frequency synthesizer

Abstract: The frequency divider includes a first or prescaling counter which selects between first and second frequency division factors, in response to a first control signal, and then divides an input signal frequency responsive to the first control signal. A second and programmable counter frequency divides the output of the first or prescaling counter by a third frequency-division factor. A third and programmable counter frequency divides the output of the first counter by a fourth frequency-division factor which is smaller than the third frequency-division factor. A switching control circuit then converts the output of the third counter and supplies the converted signal to the first counter, as the first control signal. The digital frequency divider is suitable for use a part of a phase-locked loop frequency synthesizer.

Image information storage and retrieval system

Abstract: PURPOSE:To readout information from a file directly without accessing to a host information processor and to increase a retrieval speed, by storaging information with higher retrieval frequency to the file added to an image input and output device. CONSTITUTION:A request ID information inputted from the user is inputted to an ID analysis section 2, the information is analyzed and a corresponding frequency counter from a storage section 3 is read based on the information and set to a register 4. The value n of the set frequency counter and a frequency set value N stored in a frequency set storage register 6 are compared at a comparison circuit 7. When N>n, a signal line 8 is made active, when N=n, a signal line 9, and when N =n, an AND circuit 12 is set, the information of the section 2 is added to a transmission and reception control section 13 to access a host information processor. The image information from the host is stored in a file 15 via a file control section 14 and the image information is retrieved from the section 14 without accessing to the host.

Test set for a directional command active sonobuoy system (DICASS)

Abstract: A DICASS test set utilizes a microcomputer to process infromation from an put and a down link section, generate the appropriate control logic for all the various electronic sections and format the appropriate output data for the output in uplink sections. A keyboard is provided from which an operator can input data the controller. A display and printer is provided to which the controller outputs information to the operator. The down link section consists of a UHF receiver, envelope detector, timer, filter bank, decoder, frequency counter. The uplink section consists of a reverberation simulator, a signal synthesizer, bearing, echo level and sea state controllers, three separate noise sources, multipliers and summing circuitry.

Turbo-molecular vacuum pump rotor revolution rate determn. - is by counting residual armature magnetism induced coil voltage frequency

Abstract: A method and arrangement for measuring the rate of revolution of a vacuum pump rotor are esp suitable for a turbomolecular vacuum pump driven by an electric motor with a coil and armature They enable the partic simple measurement of revolution rate The pump drive motor is switched off for a short period during which the frequency of the alternating voltage induced in the coil by residual magnetism of the armature is measured by a conventional frequency counter (11) The coil of the electric motor is either connected to the voltage source (2) or to the counter (11) via a changeover switch (8) in the motor power line (3) At least two (5,6) of the three power line phases (4,5,6) are able to be connected to the counter

Smoothness tester for paper - uses record desk with metal head replacing needle and digital vibration spectrum display

Abstract: A smoothness tester for paper enables the surface smoothness to be determined correctly and rapidly. It is a simple device which is less expensive to make and operate than conventional testers and gives more reproducible results. The surface of a paper sample rotating on a plate is scanned by a sound head. The resulting vibration spectrum is displayed digitally using a frequency counter. A sound record player is connected to the frequency counter. Its sapphire needle is replaced by a metal head. The metal head is attached to the crystal system using a two component adhesive. Its application pressure is regulated by moving an adjustable counterweight on the player arm. A metal disc of equal dia. is placed on the deck to form a base for the paper.

Phase locked loop tuning system including a prescaler conditioned to oscillate at an out-of-band frequency

Abstract: In a phase locked loop tuning system including a prescaler for dividing the frequency of the local oscillator signal by a factor selected to make the resultant frequency divided signal compatible with digital processing portions of the tuning system, a frequency selective network is coupled to the prescaler to tune the self-oscillation frequency of the prescaler to a frequency not corresponding to the local oscillator frequency of any legitimate channel. In this manner, when a new channel is selected and the amplitude of the local oscillator signal is below the threshold at which the prescaler will respond to it, the phase locked loop will properly control the local oscillator, rather than respond to a self-oscillation signal which may otherwise correspond to the local oscillator frequency for the selected channel.

Hysteresis level measuring circuit

Abstract: PURPOSE:To simplify a measuring circuit and also to stabilize measurement by measuring a hysteresis input level through conversion into a frequency of oscillation. CONSTITUTION:According to an output state of a device 7 which is an object to be measured, an arrangement is such that a sink type constant current source 11 or a source type constant current source 12 is connected to a time constant circuit 9 through an output switching circuit. A voltage value of the time constant circuit 9 works as output of a buffer supply 8 and is supplied to the device 7. Where voltage of the buffer supply 8 reaches a given level, an output of the device 7 inverts, and the output switching circuit 10 is changed again. A repeat of the operation is counted on a frequency counter 13 to obtain a value of hysteresis.

Electronic puls generator for an electricity counter.

Abstract: The pulse generator has an oscillator component (3), the frequency of which is determined by a parallel oscillatory circuit formed of inductance (1a) and capacitance, and which generates high frequency oscillations, which are passed, after rectification, to a threshold value switch. The parallel oscillatory circuit is damped by metal webs or teeth (6a), passing by the inductance (1a), of a scanning disc (6) circulating with the counter rotor axis (5), upon approximation. The passive components of the parallel oscillatory circuit are accommodated within the counter housing (4), while the oscillator component (3) with the active electronic system is disposed separately therefrom outside the lead-sealed counter housing (4) in or on the terminal block (9).

Frequency counter for musical instrument

Abstract: PURPOSE:To measure accurately even the frequency of a sound attenuating in a short time by gradually multiplying input frequency for counting. CONSTITUTION:A signal from a transducer 1 is passed through an amplifier 2 and a band-pass filter 3 and transduced into a pluse A in a wave-shaping circuit 5. The pulse A is multiplied gradually by a synthesizer consisting of PLL6 and a frequency- dividing circuit 7 and turns to be a clock pulse B of a BCD counter 8. When PLL6 is synchronized, a synchronization detecting cicuit 16 releases resetting of a frequency-dividing circuit 13. The counter 8 counts the clock pulse B and transfers data thus obtained to a memory in the counter. The data are indicated dynamically by a decoder driver 9, a digit driver 10 and an indicator 11.

Electronic parking time indicator - has clock oscillator and three stage decade counter with display

Abstract: The electronic parking disc indicates parking time in minutes, regardless of the time of the day and may comprise integrated circuits or discrete circuit elements. An I.C.- clock oscillator is connected so as to generate one minute pulses. These pulses clock a three stage decade counter counting ones, tens and hundreds input pulses up to a maximum of 199 minutes. The counters are connected to an l.e.d. or, for economy, and l.c.d. display. An additional combinational logic stops the oscillator (2240/10-1) and resets the counter (4026/15-1). Switching off the ignition starts the oscillator (2240/10-0) and enables the counter (4026/15-0).

Speed sensing circuit

Abstract: PURPOSE:To generate a speed signal without using tachogenerator, by using the output of a smoothing filter as the speed signal, and counting the number of the pulses generated by a voltage frequency converter. CONSTITUTION:When the secondary winding 101c of a resolver 101 is rotated in the forward direction by a fine mechanical angle theta deg., an error signal ERS is outputted. The ERS has a sign corresponding to the rotating direction of the secondary coil 101c, is converted into the speed signal VS which is proportional to sin(theta-alpha), where alpha=electric angle, and counts up or down a reversible counter 102a via the voltage frequency counter 110. A cosalpha generating circuit 102b and sinalpha generating circuit 102c generate the primary voltage corresponding to the contents of a counter 102a, and excite the primary windings 101a and 101b. While the secondary coil 101c is rotating at a constant speed, an error angle (theta-alpha) takes a value corresponding to the rotating speed. That is, the rotating speed is equal to the speed signal VS. In this constitution, the speed signal can be generated without using the tachogenerator and the like.

Radio receiver circuit displaying preset transmit frequencies - has programmable fixed value memory for transmit frequencies, interrogated by clock pulse generator and counter

Abstract: The circuit containing a radio receiver has manual oscillator tuning. A programmable fixed value memory (10) stores the preset transmit frequencies, and is interrogated by a clock pulse generator (11) and a counter (12) in such a manner that all stored transmit frequencies appear sequentially during a period of the clock pulse generator at the output (10A) of the memory in a cyclic manner. A frequency counter (17) measures the oscillator (16) generated frequency which also corresponds to the received transmit frequency. A comparator (13) treats the stored and received frequencies and generates a signal, on coincidence, triggering the optical or acoustic display (19). Between the frequency counter and the comparator is pref. incorporated a memory (18), set at the end of each measuring period by the frequency counter generated pulse. It also stores, during the measuring period of the frequency counter, the received transmit frequency.

Multiburst signal generation

Abstract: A multiburst test signal generator and a method for using the generator's test signal to determine the frequency response characteristics of television video circuits with a high degree of accuracy is described One of the burst frequencies is continuously enabled and made variable and the other burst frequencies are disabled The resulting continuous sine wave is applied to the circuit being tested, its frequency is varied, and the output of the circuit being tested is monitored with a conventional frequency counter

Receiving method of wireless equipment

Abstract: PURPOSE:To perform signal discrimination with a simple circuit constitution by discriminating a frequency and an access address by selecting address information with characteristic filters which correspond to modulation frequencies respectively and counting the frequency in every definite time. CONSTITUTION:In every difinite time, a signal obtained by modulating a carrier in time series is transmitted as an address signal from wireless equipment (n) times by using plural frequencies. The signal from said wireless equipment is received by antenna 1 of a receiver and applied to plural filters 41-4n via front end 2 and amplifier 3, and filters 41-4n select respectively the address signal with characteristics f1-fn that correspond to modulated signals. Outputs of those filters 41-4n are detected by level detecting circuit 5, whose detection output is counted by frequency counter 8 of logical circuit 6 and the count value is processed by signal processing circuit 9 to discriminate the frequency and access address, thereby controlling load 7.

Shift bus control system

Abstract: PURPOSE:To ensure a high-speed operation for diagnosis for the shift bus control provided to the information processor, by having the shift in the same frequency as much as possible as the number of bits of the memory elements on the shift bus which are the subjects of the shift-in or shift-out action. CONSTITUTION:The shift control part 110 gives the control to the shift-in and shift- out actions to 120 sheets of packages 101-10,128 which are the subjects of the shift- in and shift-out actions. And a test is carried out by the diagnosis processor 120 for the device including packages 101-10,128 plus the control part 110. Here a comparison 170 is given between the number of the memory elements corresponding to packages 101-10,128 and the frequency of the frequency counter 160. And when an agreement of comparison is obtained, the shift-in or shift-out action is stopped by the control circuit 23. Thus the shifting is given in the same frequency as much as possible as the number of bits of the memory elements on the shift bus which are the subjects of the shift-in or shift-out action. Accordingly, the shifting frequency can be reduced to accelerate the action of diagnosis.