Showing papers on "Logarithmic number system published in 2015"

An FPGA-Based Architecture for Local Similarity Measure for Image/Video Processing Applications

Abstract: Similarity measures are used in diverse signal-processing applications. Bhattacharyya coefficient is one of the most popular similarity measures that is widely used in many image/video processing applications. Several of these applications need to compute similarity measure between probability density functions of local image statistics. In this paper, an efficient hardware architecture is proposed for accelerating the local similarity measure (LSM) computation using Bhattacharyya coefficient. Direct hardware implementation of Bhattacharyya coefficient requires many compute-intensive hardware resources, which slow down the overall computation process. Data path of the proposed architecture utilizes fixed-point arithmetic and is based on the logarithmic number system. Fast binary logarithmic and antilogarithmic computing units are deployed to realize the required complex arithmetic operations. The histogram computation is accomplished using single-cycle read-modify-write operations on the received image data stored in DDR2 SDRAM. The proposed architecture is realized in the Virtex-5 xc5vfx70t FPGA device of Xilinx ML-507 platform. The device utilization of the implemented architecture shows that it utilizes 4.5% FPGA slices, 5.4% Block RAMs and 27.34% DSP48E slices.

Logarithmic Discrete Wavelet Transform for Medical Image Compression with Diagnostic Quality

Abstract: This paper presents a novel study of logarithmic discrete wavelet transform (DWT) for medical image compression. It proposes a new technique to compute the DWT using the logarithmic number system (LNS) instead of floating point arithmetic. It investigates its impact on the image quality which is an essential factor for medical images to avoid any misdiagnose. The paper presents detailed experimental results for three medical images modalities: CT, MRI and X-Ray. The results show that the LNS approach gives a significant improvement in the image quality measured with the structural similarity index (SSIM).

Arithmetic addition and subtraction function of logarithmic number system in positive region: An investigation

Abstract: Logarithmic number system or LNS has become an optimal choice in digital image processing instead of floating point (FP) system based on latest researches in LNS. Digital image processing which deals with a lot of complex operations such as multiplication and division, makes LNS as a great choice of implementation. However, the implementation had been restricted by the addition and subtraction function in LNS arithmetic as these functions entail complex procedures and circuitry. As its huge potential to be a substitution of FP, there is an urgent need for LNS to improve the performance of both operations. Hence, various studies had been conducted in this area, however most of the research concern the implementation of these operations in the negative region. Therefore, this study is conducted with the objective on the exploration of both LNS addition and subtraction operations in the positive region and highlights the potential areas for design modifications and improvements. Then, these enhancements will be combined with other arithmetic functions in creating an optimum LNS design to be utilized in any digital image processing system.

Design and implementation of complex arithmetic operations using binary logarithmic number system

Abstract: Now a day's various real time applications and image processing applications requires hardware that can perform various complex arithmetic operations. These operations can be performed by using binary logarithmic number system. This paper includes binary logarithmic circuit based on FPGA. Above architecture uses combinational logic circuit elements and fixed point data path number format. The architecture is able to calculate the logarithm of integer number, fractional number and integer fractional number. This architecture is designed in Xilinx Virtex-5 device. This architecture consumes minimal FPGA resources that are shown by device utilization summary. Finally error analysis is done which shows that architecture has minimal number of errors considering fractional number and fixed point numbers.

An Efficient Low Power Log Based FPU Design for FPGAs

Abstract: All new technical developments generally arise with complex problems demanding numerals that have more credence than normal integers this offer a great importance to the real valued floating point numbers. Though the arithmetic computation on these numbers are quite complex than normal integer based computations, the existing floating point units (FPUs) use only integer based computation units with slight modification in the floating point standards for arithmetic computations. Using these normal integer styled multipliers in the FPUs consume more power because of increased operation strength, this also leads to reduction in accuracy due to truncations. These factors induce the proposal of new design for FPU with modified multiplier circuitry to give good accuracy by consuming minimal area and power. Hence a low power Logarithmic Number System (LNS) is adopted for the model, but LNS suffers serious drawback of increased complexity in addition. So a segregator unit is suggested for partial employment of LNS in the model, further width of the log codes provokes accuracy of the model. Thus designed model is tested and compared for its efficiency by implementing in Xilinx field-programmable gate array (FPGA) device and compared with similarly implemented existing model. From the result it is found the suggested model achieves 71% accuracy with 24.8% less area utilized than normal integer based computation structures in field programming gate arrays (FPGAs).

An error-compensated piecewise linear logarithmic arithmetic unit for phong lighting acceleration

Abstract: This paper presents an error compensated piecewise linear logarithmic arithmetic unit for Phong lighting hardware acceleration. Two novel error compensation techniques have been applied to differentiate finer bounds within piecewise linear (PWL) approximation intervals to achieve a lower absolute mean error rate with minimal increment in resource costs. Area/power/error performances of the logarithmic unit designs are presented for the proposed topologies applied to a five-interval base-2 PWL logarithm approximation circuit in comparison to its baseline counterpart. In addition, the design is applied to a single-cycle Phong lighting hardware accelerator and evaluated for graphical estimation accuracy at the system-level.