Showing papers on "Memory controller published in 1973"

Concurrent data address and refresh control for a volatile lsi memory system

Abstract: A novel internal organization of an LSI memory chip for optimum refresh control is disclosed. The chip is organized in a plurality of N similar memory loops in which the M data bits that are stored in each memory loop are serially shifted therethrough in an end-around fashion for the data reading, writing and refreshing operations. The novel internal organization includes partitioning the N memory loops into S subgroups of 2n memory loops per subgroup, N = S2n, where n is a positive integer of 0 or greater and then refreshing the 2n memory loops of each of the S subgroups at a refresh clock signal frequency FR that is a submultiple of the fundamental data clock signal frequency FD, FD = SFR, at which the normal data read/write operations are performed. A fundamental data clock signal source of frequency FD drives a refresh clock signal source that sequentially and continuously refreshes each of the N memory loops at the refresh clock frequency FR using the internal selection gates of the LSI memory chip rather than using the internal memory loop address decoder; this permits the refresh operation to be an entirely internal operation independent of external memory control.