Showing papers on "Memory refresh published in 2023"
TL;DR: In this paper , a review of the SRAM cell architecture with different technique and in low power applications is presented, where the authors show that power consumption may be reduced by utilizing nonconventional device architectures, innovative circuit topologies & architectural optimization techniques, among other things.
2 citations
01 Jan 2023
TL;DR: In this article , a review of various techniques used in the above mentioned topics their problems and effective solution, advantages disadvantages, few analyses, and its application is presented, including merging of logic and DYNAMIC RAM, various trends of megabit, the era of gigabits, and newly advanced 3D DRAM technology.
Abstract: DYNAMIC RAM or dynamic random-access memory (Dynamic RAM) is a type of random-access semiconductor memory in which a bit of data get stored into the memory cells which consist of capacitors and transistors. In digital electronics DYNAMIC, RAM technology is widely used with the requirement of low cost and higher memory capacity. With the newly emerging techniques, technology, challenges in DYNAMIC RAM technologies problem of high energy consumption, leak aging, etc., also rise. In this research paper, we will be able to know about DYNAMIC RAM, various fields of DYNAMIC RAM, such as merging of logic and DYNAMIC RAM, various trends of megabit, the era of gigabits, and newly advanced 3D DYNAMIC RAM technology. In this review, we learn about various techniques used in the above mentions topics their problems and effective solution, advantages disadvantages, few analyses, and its application.
TL;DR: In this article , a comparative analysis of various available SRAM cell architectures under various design constraints is presented, and the effect of supply voltage scaling over the various memory cells is also shown.
TL;DR: In this paper , a brain-like transistor memory with triple operation modes (i.e., sensory, short-term, and long-term memory) was developed by doping the dielectric layer with multistimuli responsive donor-acceptor Stenhouse adducts.
Abstract: Human brain simultaneously gains sensory memory, short-term memory, and long-term memory, which allows information from the outside world to be sensed in the form of chemical and physical stimuli and enables highly efficient information storage, exchange, and processing. Such intelligent memory behavior guarantees human beings to not only solve the most complicated tasks but also rapidly respond to external environments. Developing brain-like memory with versatile data-storage modes plays an increasingly important role in modern information technologies. However, traditional memory devices generally only show one single mode of memory and suffer from poor tunability. To this end, here we develop a brain-like transistor memory with triple operation modes (i.e., sensory, short-term, and long-term memory) by doping the dielectric layer with multistimuli responsive donor–acceptor Stenhouse adducts. When been written with humidity, the transistor behaves like a “sensory memory” as the data fade immediately upon humidity removal. When been written with light, the transistor exhibits a volatile memory and could be erased by heating, analogous to the “short-term memory.” Further, when the transistor is programmed by heat or electrical field, a long-term memory is created. This work opens a new door to design intelligent memories for advanced applications.
01 Jan 2023
11 Apr 2023
TL;DR: In this article , an analysis of a Logic-In-Memory (LiM) memory array with three memory cell variants is presented, and the performance is compared to SRAM and CAM memories.
Abstract: The speed of modern digital systems is severely limited by memory latency (the ``Memory Wall'' problem). Data exchange between Logic and Memory is also responsible for a large part of the system energy consumption. Logic--In--Memory (LiM) represents an attractive solution to this problem. By performing part of the computations directly inside the memory the system speed can be improved while reducing its energy consumption. LiM solutions that offer the major boost in performance are based on the modification of the memory cell. However, what is the cost of such modifications? How do these impact the memory array performance? In this work, this question is addressed by analysing a LiM memory array implementing an algorithm for the maximum/minimum value computation. The memory array is designed at physical level using the FreePDK $\SI{45}{
ano\meter}$ CMOS process, with three memory cell variants, and its performance is compared to SRAM and CAM memories. Results highlight that read and write operations performance is worsened but in--memory operations result to be very efficient: a 55.26\% reduction in the energy--delay product is measured for the AND operation with respect to the SRAM read one; therefore, the LiM approach represents a very promising solution for low--density and high--performance memories.
15 Jan 2023
TL;DR: The first non-volatile memory cell composed entirely of MEM relays that does not need CMOS circuitry for reading or writing was reported in this paper , which uses a 7-terminal nonvolatile relay for information storage and two 3-tolerant relays for read and write access.
Abstract: This paper reports the first non-volatile memory cell composed entirely of MEM relays that does not need CMOS circuitry for reading or writing. The cell uses a 7-terminal non-volatile relay for information storage and two 3-terminal relays for read and write access. This three-relay cell has been fabricated and characterised to demonstrate read and write operations. The cell architecture has been designed such that multiple cells can be tiled in combination with a relay-based multiplexer to make a digital all MEM reprogrammable non-volatile memory. Such a memory will have near zero standby power and ability to operate in harsh environments beyond the capabilities of conventional memory technologies.