Showing papers on "Noisy-channel coding theorem published in 2023"
TL;DR: In this paper , a turbo encoder and decoder hardware chip was designed and analyzed for a field-programmable gate array (FPGA) hardware chip and its performance was evaluated using hardware and timing parameters extracted from Xilinx ISE 14.7.
Abstract: Turbo codes are error-correcting codes with performance that is close to the Shannon theoretical limit (SHA). The motivation for using turbo codes is that the codes are an appealing mix of a random appearance on the channel and a physically realizable decoding structure. The communication systems have the problem of latency, fast switching, and reliable data transfer. The objective of the research paper is to design and turbo encoder and decoder hardware chip and analyze its performance. Two convolutional codes are concatenated concurrently and detached by an interleaver or permuter in the turbo encoder. The expected data from the channel is interpreted iteratively using the two related decoders. The soft (probabilistic) data about an individual bit of the decoded structure is passed in each cycle from one elementary decoder to the next, and this information is updated regularly. The performance of the chip is also verified using the maximum a posteriori (MAP) method in the decoder chip. The performance of field-programmable gate array (FPGA) hardware is evaluated using hardware and timing parameters extracted from Xilinx ISE 14.7. The parallel concatenation offers a better global rate for the same component code performance, and reduced delay, low hardware complexity, and higher frequency support.
TL;DR: In this article , the authors proposed a method to derive equivalent coding structures of elements to construct low density parity check (LDPC) codes, which is expected to be beneficial for short block-length transmissions, but providing high coding rate.
Abstract: This paper proposes a method to derive equivalent coding structures of elements to construct low density parity check (LDPC) codes. We propose stairs LDPC (SLDPC) codes to demonstrate the effectiveness of the proposed method, which is expected to be beneficial for short block-length transmissions, but providing high coding rate. The equivalent coding structures are both for transmitter and receiver to: (i) reduce the encoding and decoding computational complexity, and (ii) search possibility of finding new coding scheme and observe their performances. We evaluate the validity of the method by confirming the equality in performances of the SLDPC codes in terms of bit-error-rate (BER) followed by investigation on their performance gaps to the Shannon limit via a series of computer simulations. The results show that the SLDPC codes have the same BER performance with that of the low density generator matrix (LDGM) codes confirming the validity of the proposed equivalent matrix derivation. This result indicates that different graphs can provide the same performances, because their equivalent matrices are the same. This result is expected to open new insight for the designing simple channel coding for short block-length LDPC codes having high coding rate for future less power consumption applications.