Showing papers on "Program counter published in 1971"

Data processor with parallel operations per instruction

Abstract: An electronic digital data processor particularly useful for performing tasks requiring substantial list processing computation in real (or neat real) time The processor is organized in a manner which permits multiple operations, including arithmetic and data transfer operations, to be executed in parallel at each clock time in response to a single instruction drawn from an instruction memory This parallel operation is achieved as a consequence of implementing the internal data registers and arithmetic circuits with multiple data inputs and by controlling them in response to a particular instruction format Data is held constantly available at each register input bit position The particular data input selected at any clock time for transfer into a register is determined by the particular instruction concurrently contained within an instruction buffer register Instructions are drawn one at a time into the instruction buffer from a high speed internal instruction memory which in turn is normally loaded, one instruction block at a time, from a core memory The instruction format includes multiple fields which separately identify operations to be executed in parallel

Program control apparatus

Abstract: Program control apparatus in which current instruction execution and next instruction fetch occur in overlapped time periods during one instruction cycle. The results of a previous instruction execution are employed to set or not set selected ones of a plurality of condition latches in accordance with a current instruction. The current instruction also includes a test code which when combined in a decoding network with the outputs of the latches will produce a selection signal to a next instruction address multiplexer. The multiplexer will respond thereto to selectively couple one of plural instruction address sources to an instruction address buss. The program control apparatus also includes means responsive to a current instruction test code and the outputs of the condition latches to enable or to inhibit the storage of the results of an instruction execution.

Apparatus and method for controlling sequential execution of instructions and nesting of subroutines in a data processor

Abstract: A stack pointer for identifying one of a group of instruction word address registers in a data processor. To fetch a new instruction, the stack pointer is examined to identify the instruction word address register to be used. The address contained in this register is then incremented to derive the address of the new instruction to be executed. A branch instruction causes the stack pointer to be incremented and the base address of the new subroutine to be loaded into the instruction word address register newly identified by the stack pointer. An exit instruction causes the stack pointer to be decremented. Exit-and-branch instructions are possible because the stack pointer counts in a closed loop in both directions, there being no ''''first'''' or ''''last'''' instruction word address register.

Method and apparatus for applying source language statements to a digital computer

Abstract: A method of operating a general purpose computer which uses instruction words, each containing, in addition to an operation code and an operand address code, an operation sequence code and an improved processor adapted to the contemplated method is shown The operation sequence code in each instruction word is read out of memory as a program counter is sequenced so that the processor may be caused to defer the operation called for by the instruction word until such operation may properly be executed In addition, the processor may be controlled so that deferral may be effected whenever the hierarchal precedence of an operation to be performed dictates that the next following operation in a sequence be performed first

Digital computer having a plurality of accumulator registers

Abstract: In a programmable digital computer containing a plurality of accumulator registers, an accumulator address register for placing one accumulator register or another into operation, a plurality of instruction counters and an instruction counter address register for selectively operating one instruction counter or another, an addition/subtraction circuit is provided for automatically adding or subtracting unity to the number in the accumlulator address register and/or the instruction counter address register in dependence on the contents of the address part of the program instruction words.