Showing papers on "Root-raised-cosine filter published in 2021"

Efficient MODEM Design For SDR Application

Abstract: Efficient modulation and demodulation(MODEM) design is required and essential for Software defined radio (SDR) application. In the proposed design not only reducing the hardware complexity but it will reduce the power consumption also. Optimization of the MODEM hardware is done through three important design metrics through time (speed / frequency), power consumption and area(size). To develop a product that can transmit the signal to a longer distance without loss of original information with high bandwidth. Also to develop a smart MODEM system that can consume very less area and power. The project aims at presenting a method to design an efficient QPSK modulator and demodulator system with and without AWGN(Additive white Gaussian Noise) and RRC filter (Root Raised cosine filter) for SDR application. The entire QPSK system has been simulated in Xilinx 14.7 version software and Vivado software. Finally implemented on to the Spartan 6 FPGA Board and Zynq 7000 based ZED board. the results depicts that the proposed design can greatly improve the speed and reduce the latency and improve the frequency of operation about 20% when compared with the existing method.

Design and Implementation of a Digital Front-End With Digital Compensation for Low-Complexity 4G Radio Transceivers

Abstract: A digital front-end with digital compensation is designed and implemented for low-complexity 4G radio transceivers targeted for wearable devices such as smart watches. The proposed digital front-end in the radio receiver consists of an anti-drooping filter, a decimation chain, a DC offset cancellation circuit, and an in-phase and quadrature estimation and compensation circuit whereas the digital front-end in the radio transmitter includes an anti-drooping filter, a root raised cosine filter, and an interpolation chain. The proposed DC offset cancellation circuit is based on both infinite-duration impulse response filter and moving average. The proposed in-phase and quadrature estimation and compensation circuit attains lower complexity with negligible performance loss, compared with an existing circuit. A systematic top-down strategy is taken to design and implement the proposed digital front-end from the algorithm level to the application-specific integrated circuit or ASIC hardware level. The inter-symbol interference in the transmitter and the receiver is analyzed and the unwanted emission in the transmitter is simulated as well. For all the seven bandwidths or modes in 3G and 4G, the digital front end receiver ASIC satisfies all the interference requirements, namely, in-band blocker, narrowband blocker, and adjacent channel selectivity requirements whereas the digital front end transmitter ASIC meets all the unwanted emission requirements, namely, spectrum emission mask, spurious emission, and adjacent channel leakage ratio requirements. The proposed multimode 4G digital front end receiver and transmitter ASICs exhibit a >40dB mean signal-to-noise ratio for all the seven modes and are implemented in a 180nm CMOS process technology.