Showing papers on "Serial port published in 1981"

Wafer-scale integrated circuits

Abstract: A wafer-scale integrated circuit wherein a plurality of memory cells on a wafer are connectable from a port to form a chain memory looping away from and back to the port by means of a serial connection of forward moving data registers and a serial connection of backward moving data registers between cells, has a reduced risk of any individual, otherwise functional cell being non-functional as a result of a failure elsewhere on the wafer of an associated global signal line by achieving a reduction in the numbers of global lines by providing the clock signal for controlling the shifting of data in the registers between the cells in parallel with the data, the inter-cell clock operating a multiple clock pulse generator in each cell.

Improvements in or relating to wafer scale integrated circuits

Abstract: A wafer scale integrated circuit wherein a plurality of data processing cells (12), such as memory cells, all on a single wafer (10) are connectable into a chain (18) starting at a port (14) for passing data away from the port (16) via a serial connection of forward registers (38) and back towards the port (14) via a serial connection of reverse registers (40), has a reduced risk of any individual, otherwise perfect cell (12) being non-functional as a result of a failure elsewhere on the wafer (10) of an associated Global line by achieving a reduction in the number of Global lines required by providing a data shift controlling master clock signal which is transferred between the cells (12) in parallel with the data and is used to operate a multiple clock generator (46) in each cell.

Serial interface device

Abstract: PURPOSE:To enable to connect conventional terminal units to the time sharing multiplex transmission system easily, by independently providing the serial interface device having the address discriminating function and transmission speed conversion function and so on from the terminal device main body. CONSTITUTION:The conventional terminal device 201 without the address discrimination function is connected to the transmission line via the serial interface device 30 with the required function such as address discriminating function and transmission speed conversion function separately provided. Thus, the same as the terminal devices 202-20n exclusive use for the transmission system having the address discriminating function, the address specific to the terminal device 201 is assigned. The interface device 30 is driven by the central processing unit 10 designating the device address, allowing to give and receive the data between the terminal device 301 and the central processing unit 10 by way of the interface device 30.

A CAMAC Serial Crate Controller for the Tevatron Accelerator

Abstract: A CAMAC serial crate controller has been developed for the Tevatron Accelerator Control System. The controller accommodates two serial ports of access, block transfer read facility, and aggregate command capability. Communications to the controller are bit serial at a 10 megabit rate and employ a specially developed protocol. The programmed serial ports allow better than 50K dataway operations per second. The Block Transfer read facility operates in the UQC mode and can perform at the rate of 250K dataway operations per second. Operations at both ports and the Block Transfer function may be fully interleaved. The design provides for programmed arbitration of the two serial ports allowing either port to reserve the crate or a target slot for an uninterrupted sequence of dataway operations.