Showing papers on "Synchronous Data Flow published in 2003"

HEMLOCK: HEterogeneous ModeL Of Computation Kernel for SystemC

Abstract: As SystemC gains popularity as a System Level Design Language (SLDL) for SystemOn-Chip (SOC) designs, heterogeneous modelling and efficient simulation become increasingly important. The key in making an SLDL heterogeneous is the facility to express different Models Of Computation (MOC). Currently, all SystemCmodels employ a Discrete-Event simulation kernel making it difficult to express most MOCs without specific designer guidelines. This often makes it unnatural to express different MOCs in SystemC. For the simulation framework, this sometimes results in unnecessary delta cycles formodels away from theDiscrete-EventMOC, hindering the simulation performance of themodel. Our goal is to extend SystemC’s simulation framework to allow for better modelling expressiveness and efficiency for the Synchronous Data Flow (SDF) MOC. The SDFMOC follows a paradigmwhere the production and consumption rates of data by a function block are known a priori. These systems are common in Digital Signal Processing applications where relative sample rates are specified for every component. Knowledge of these rates enables the use of static scheduling. When compared to dynamic scheduling of SDFmodels, we experience a noticeable improvement in simulation efficiency. We implement an extension to the SystemC kernel that exploits such static scheduling for SDF models and propose designer style guidelines for modelers to use this extension. The modelling paradigm becomes more natural to SDF which results to better simulation efficiency. We will distribute our implementation to the SystemC community to demonstrate that SystemC can be a heterogeneous SLDL.

Multithreaded Synchronous Data Flow Simulation

Abstract: This paper introduces an efficient multithreaded synchronous dataflow (SDF) scheduler that can significantly reduce the running time of multi-rate SDF simulations on multiprocessor machines with only a slight increase of memory usage over standard cluster loop scheduler. Experiments run on a dual processor machine achieve on average approximately 146% increase in performance with less than 2.4% increase in memory usage. There is an average of 2/spl times/ speedup with a quad processor machine.