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Showing papers on "Triple DES published in 1991"


Patent
26 Dec 1991
TL;DR: In this article, the authors present an encryption/decryption and authentication algorithm, which has three major steps: the first step is to generate cipher text, the second step is generating the authentication field, and the third step is encrypting or deciphering the appropriate data in the message.
Abstract: In one embodiment, the present invention is an encryption/decryption and authentication algorithm. The algorithm has three major steps. The first step is generating cipher text. The second step is generating the authentication field. The third step is encrypting or deciphering the appropriate data in the message. One byte of cipher text is generated for every byte of plain text contained in the message. After all the cipher text is generated, a four byte authentication field is generated using the last four bytes of cipher text. The message is then scanned for data fields which have been encrypted or are to be encrypted and the corresponding byte of cipher text replaces the message bytes. The encryption is accomplished by sending the cipher text instead of message text. To decipher the message, the algorithm operates in a reverse mode to replace the cipher text with the message text, i.e., the algorithm is a self-reversing process.

70 citations


Proceedings ArticleDOI
H. Bonnenberg1, A. Curiger1, Norbert Felber1, Hubert Kaeslin1, X. Lai1 
14 Oct 1991
TL;DR: The high speed architecture for a VLSI implementation of a new smart-key block cipher is presented, which performs data encryption and decryption in a single hardware unit with a maximum clock frequency of 33 MHz.
Abstract: The high speed architecture for a VLSI implementation of a new smart-key block cipher is presented. The chip performs data encryption and decryption in a single hardware unit. It runs with a maximum clock frequency of 33 MHz permitting a data conversion rate of more than 55 Mb/s. This high data rate, compared to currently available DES (data encryption standard) implementations, has been achieved by implementing a pipelined architecture and by using a sophisticated data scheduling scheme guaranteeing a continuously fully loaded pipeline. >

23 citations


Patent
18 Sep 1991
TL;DR: In this article, the authors proposed a session key sharing scheme to eliminate the need of decoding processing between communicators while confirming it by communicators of each other by using secret key data and operated cipher data.
Abstract: PURPOSE:To eliminate a need of decoding processing to share a session key between communicators while confirming it by communicators of each other. CONSTITUTION:An information processing terminal 100 and an IC card 110 transmit generated random numbers 10 and 20 to each other and cipher the transmitted random numbers to obtain cipher data 12 and 22. Thereafter, they cipher received random numbers of each other to transmit cipher data 24 and 14. They compare received cipher data and data ciphered by themselves with each other; and in the case of coincidence, they use secret key data and operated cipher data to obtain key data common to them by operation.

20 citations


Journal ArticleDOI
TL;DR: A long-standing proposal for modifying cipher block chaining to prevent data expansion is shown to be insecure in some circumstances and different modifications are presented which appear secure.

4 citations